mirror of https://gitee.com/openkylin/linux.git
533 lines
13 KiB
C
533 lines
13 KiB
C
/*
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/initval.h>
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#include "jz4740-i2s.h"
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#include "jz4740-pcm.h"
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#define JZ_REG_AIC_CONF 0x00
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#define JZ_REG_AIC_CTRL 0x04
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#define JZ_REG_AIC_I2S_FMT 0x10
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#define JZ_REG_AIC_FIFO_STATUS 0x14
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#define JZ_REG_AIC_I2S_STATUS 0x1c
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#define JZ_REG_AIC_CLK_DIV 0x30
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#define JZ_REG_AIC_FIFO 0x34
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#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
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#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
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#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
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#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
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#define JZ_AIC_CONF_I2S BIT(4)
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#define JZ_AIC_CONF_RESET BIT(3)
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#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
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#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
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#define JZ_AIC_CONF_ENABLE BIT(0)
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#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
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#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
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#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
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#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
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#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
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#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
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#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
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#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
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#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
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#define JZ_AIC_CTRL_FLUSH BIT(8)
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#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
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#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
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#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
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#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
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#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
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#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
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#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
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#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
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#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
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#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
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#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
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#define JZ_AIC_I2S_FMT_MSB BIT(0)
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#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
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#define JZ_AIC_CLK_DIV_MASK 0xf
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struct jz4740_i2s {
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struct resource *mem;
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void __iomem *base;
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dma_addr_t phys_base;
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struct clk *clk_aic;
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struct clk *clk_i2s;
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struct jz4740_pcm_config pcm_config_playback;
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struct jz4740_pcm_config pcm_config_capture;
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};
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static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
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unsigned int reg)
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{
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return readl(i2s->base + reg);
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}
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static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
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unsigned int reg, uint32_t value)
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{
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writel(value, i2s->base + reg);
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}
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static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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uint32_t conf, ctrl;
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if (dai->active)
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return 0;
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ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
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ctrl |= JZ_AIC_CTRL_FLUSH;
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jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
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clk_enable(i2s->clk_i2s);
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf |= JZ_AIC_CONF_ENABLE;
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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return 0;
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}
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static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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uint32_t conf;
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if (dai->active)
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return;
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf &= ~JZ_AIC_CONF_ENABLE;
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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clk_disable(i2s->clk_i2s);
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}
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static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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uint32_t ctrl;
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uint32_t mask;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
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else
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mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
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ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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ctrl |= mask;
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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ctrl &= ~mask;
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break;
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default:
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return -EINVAL;
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}
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jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
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return 0;
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}
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static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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uint32_t format = 0;
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uint32_t conf;
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
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format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
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break;
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case SND_SOC_DAIFMT_CBM_CFS:
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conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
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break;
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case SND_SOC_DAIFMT_CBS_CFM:
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conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_MSB:
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format |= JZ_AIC_I2S_FMT_MSB;
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break;
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case SND_SOC_DAIFMT_I2S:
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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default:
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return -EINVAL;
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}
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
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return 0;
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}
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static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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enum jz4740_dma_width dma_width;
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struct jz4740_pcm_config *pcm_config;
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unsigned int sample_size;
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uint32_t ctrl;
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ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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sample_size = 0;
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dma_width = JZ4740_DMA_WIDTH_8BIT;
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break;
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case SNDRV_PCM_FORMAT_S16:
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sample_size = 1;
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dma_width = JZ4740_DMA_WIDTH_16BIT;
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break;
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default:
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
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ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
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if (params_channels(params) == 1)
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ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
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else
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ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
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pcm_config = &i2s->pcm_config_playback;
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pcm_config->dma_config.dst_width = dma_width;
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} else {
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ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
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ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
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pcm_config = &i2s->pcm_config_capture;
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pcm_config->dma_config.src_width = dma_width;
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}
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jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
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snd_soc_dai_set_dma_data(dai, substream, pcm_config);
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return 0;
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}
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static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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unsigned int freq, int dir)
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{
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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struct clk *parent;
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int ret = 0;
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switch (clk_id) {
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case JZ4740_I2S_CLKSRC_EXT:
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parent = clk_get(NULL, "ext");
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clk_set_parent(i2s->clk_i2s, parent);
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break;
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case JZ4740_I2S_CLKSRC_PLL:
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parent = clk_get(NULL, "pll half");
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clk_set_parent(i2s->clk_i2s, parent);
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ret = clk_set_rate(i2s->clk_i2s, freq);
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break;
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default:
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return -EINVAL;
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}
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clk_put(parent);
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return ret;
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}
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static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
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{
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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uint32_t conf;
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if (dai->active) {
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf &= ~JZ_AIC_CONF_ENABLE;
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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clk_disable(i2s->clk_i2s);
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}
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clk_disable(i2s->clk_aic);
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return 0;
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}
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static int jz4740_i2s_resume(struct snd_soc_dai *dai)
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{
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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uint32_t conf;
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clk_enable(i2s->clk_aic);
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if (dai->active) {
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clk_enable(i2s->clk_i2s);
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf |= JZ_AIC_CONF_ENABLE;
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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}
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return 0;
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}
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static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
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{
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struct jz4740_dma_config *dma_config;
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/* Playback */
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dma_config = &i2s->pcm_config_playback.dma_config;
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dma_config->src_width = JZ4740_DMA_WIDTH_32BIT;
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dma_config->transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE;
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dma_config->request_type = JZ4740_DMA_TYPE_AIC_TRANSMIT;
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dma_config->flags = JZ4740_DMA_SRC_AUTOINC;
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dma_config->mode = JZ4740_DMA_MODE_SINGLE;
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i2s->pcm_config_playback.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
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/* Capture */
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dma_config = &i2s->pcm_config_capture.dma_config;
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dma_config->dst_width = JZ4740_DMA_WIDTH_32BIT;
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dma_config->transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE;
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dma_config->request_type = JZ4740_DMA_TYPE_AIC_RECEIVE;
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dma_config->flags = JZ4740_DMA_DST_AUTOINC;
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dma_config->mode = JZ4740_DMA_MODE_SINGLE;
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i2s->pcm_config_capture.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
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}
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static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
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{
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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uint32_t conf;
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clk_enable(i2s->clk_aic);
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jz4740_i2c_init_pcm_config(i2s);
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conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
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(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
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JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
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JZ_AIC_CONF_I2S |
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JZ_AIC_CONF_INTERNAL_CODEC;
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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return 0;
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}
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static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
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{
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struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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clk_disable(i2s->clk_aic);
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return 0;
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}
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static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
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.startup = jz4740_i2s_startup,
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.shutdown = jz4740_i2s_shutdown,
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.trigger = jz4740_i2s_trigger,
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.hw_params = jz4740_i2s_hw_params,
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.set_fmt = jz4740_i2s_set_fmt,
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.set_sysclk = jz4740_i2s_set_sysclk,
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};
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#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE)
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static struct snd_soc_dai_driver jz4740_i2s_dai = {
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.probe = jz4740_i2s_dai_probe,
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.remove = jz4740_i2s_dai_remove,
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.playback = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = JZ4740_I2S_FMTS,
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},
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.capture = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = JZ4740_I2S_FMTS,
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},
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.symmetric_rates = 1,
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.ops = &jz4740_i2s_dai_ops,
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.suspend = jz4740_i2s_suspend,
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.resume = jz4740_i2s_resume,
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};
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static const struct snd_soc_component_driver jz4740_i2s_component = {
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.name = "jz4740-i2s",
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};
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static int jz4740_i2s_dev_probe(struct platform_device *pdev)
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{
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struct jz4740_i2s *i2s;
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int ret;
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i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
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if (!i2s)
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return -ENOMEM;
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i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!i2s->mem) {
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ret = -ENOENT;
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|
goto err_free;
|
|
}
|
|
|
|
i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
|
|
pdev->name);
|
|
if (!i2s->mem) {
|
|
ret = -EBUSY;
|
|
goto err_free;
|
|
}
|
|
|
|
i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
|
|
if (!i2s->base) {
|
|
ret = -EBUSY;
|
|
goto err_release_mem_region;
|
|
}
|
|
|
|
i2s->phys_base = i2s->mem->start;
|
|
|
|
i2s->clk_aic = clk_get(&pdev->dev, "aic");
|
|
if (IS_ERR(i2s->clk_aic)) {
|
|
ret = PTR_ERR(i2s->clk_aic);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
|
|
if (IS_ERR(i2s->clk_i2s)) {
|
|
ret = PTR_ERR(i2s->clk_i2s);
|
|
goto err_clk_put_aic;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, i2s);
|
|
ret = snd_soc_register_component(&pdev->dev, &jz4740_i2s_component,
|
|
&jz4740_i2s_dai, 1);
|
|
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register DAI\n");
|
|
goto err_clk_put_i2s;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_clk_put_i2s:
|
|
clk_put(i2s->clk_i2s);
|
|
err_clk_put_aic:
|
|
clk_put(i2s->clk_aic);
|
|
err_iounmap:
|
|
iounmap(i2s->base);
|
|
err_release_mem_region:
|
|
release_mem_region(i2s->mem->start, resource_size(i2s->mem));
|
|
err_free:
|
|
kfree(i2s);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int jz4740_i2s_dev_remove(struct platform_device *pdev)
|
|
{
|
|
struct jz4740_i2s *i2s = platform_get_drvdata(pdev);
|
|
|
|
snd_soc_unregister_component(&pdev->dev);
|
|
|
|
clk_put(i2s->clk_i2s);
|
|
clk_put(i2s->clk_aic);
|
|
|
|
iounmap(i2s->base);
|
|
release_mem_region(i2s->mem->start, resource_size(i2s->mem));
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
kfree(i2s);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver jz4740_i2s_driver = {
|
|
.probe = jz4740_i2s_dev_probe,
|
|
.remove = jz4740_i2s_dev_remove,
|
|
.driver = {
|
|
.name = "jz4740-i2s",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(jz4740_i2s_driver);
|
|
|
|
MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
|
|
MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:jz4740-i2s");
|