mirror of https://gitee.com/openkylin/linux.git
189 lines
4.6 KiB
C
189 lines
4.6 KiB
C
/*
|
|
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
|
* Author: Andrzej Haja <a.hajda@samsung.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* Device Tree binding constants for Exynos5420 clock controller.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
|
|
#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
|
|
|
|
/* core clocks */
|
|
#define CLK_FIN_PLL 1
|
|
#define CLK_FOUT_APLL 2
|
|
#define CLK_FOUT_CPLL 3
|
|
#define CLK_FOUT_DPLL 4
|
|
#define CLK_FOUT_EPLL 5
|
|
#define CLK_FOUT_RPLL 6
|
|
#define CLK_FOUT_IPLL 7
|
|
#define CLK_FOUT_SPLL 8
|
|
#define CLK_FOUT_VPLL 9
|
|
#define CLK_FOUT_MPLL 10
|
|
#define CLK_FOUT_BPLL 11
|
|
#define CLK_FOUT_KPLL 12
|
|
|
|
/* gate for special clocks (sclk) */
|
|
#define CLK_SCLK_UART0 128
|
|
#define CLK_SCLK_UART1 129
|
|
#define CLK_SCLK_UART2 130
|
|
#define CLK_SCLK_UART3 131
|
|
#define CLK_SCLK_MMC0 132
|
|
#define CLK_SCLK_MMC1 133
|
|
#define CLK_SCLK_MMC2 134
|
|
#define CLK_SCLK_SPI0 135
|
|
#define CLK_SCLK_SPI1 136
|
|
#define CLK_SCLK_SPI2 137
|
|
#define CLK_SCLK_I2S1 138
|
|
#define CLK_SCLK_I2S2 139
|
|
#define CLK_SCLK_PCM1 140
|
|
#define CLK_SCLK_PCM2 141
|
|
#define CLK_SCLK_SPDIF 142
|
|
#define CLK_SCLK_HDMI 143
|
|
#define CLK_SCLK_PIXEL 144
|
|
#define CLK_SCLK_DP1 145
|
|
#define CLK_SCLK_MIPI1 146
|
|
#define CLK_SCLK_FIMD1 147
|
|
#define CLK_SCLK_MAUDIO0 148
|
|
#define CLK_SCLK_MAUPCM0 149
|
|
#define CLK_SCLK_USBD300 150
|
|
#define CLK_SCLK_USBD301 151
|
|
#define CLK_SCLK_USBPHY300 152
|
|
#define CLK_SCLK_USBPHY301 153
|
|
#define CLK_SCLK_UNIPRO 154
|
|
#define CLK_SCLK_PWM 155
|
|
#define CLK_SCLK_GSCL_WA 156
|
|
#define CLK_SCLK_GSCL_WB 157
|
|
#define CLK_SCLK_HDMIPHY 158
|
|
|
|
/* gate clocks */
|
|
#define CLK_ACLK66_PERIC 256
|
|
#define CLK_UART0 257
|
|
#define CLK_UART1 258
|
|
#define CLK_UART2 259
|
|
#define CLK_UART3 260
|
|
#define CLK_I2C0 261
|
|
#define CLK_I2C1 262
|
|
#define CLK_I2C2 263
|
|
#define CLK_I2C3 264
|
|
#define CLK_I2C4 265
|
|
#define CLK_I2C5 266
|
|
#define CLK_I2C6 267
|
|
#define CLK_I2C7 268
|
|
#define CLK_I2C_HDMI 269
|
|
#define CLK_TSADC 270
|
|
#define CLK_SPI0 271
|
|
#define CLK_SPI1 272
|
|
#define CLK_SPI2 273
|
|
#define CLK_KEYIF 274
|
|
#define CLK_I2S1 275
|
|
#define CLK_I2S2 276
|
|
#define CLK_PCM1 277
|
|
#define CLK_PCM2 278
|
|
#define CLK_PWM 279
|
|
#define CLK_SPDIF 280
|
|
#define CLK_I2C8 281
|
|
#define CLK_I2C9 282
|
|
#define CLK_I2C10 283
|
|
#define CLK_ACLK66_PSGEN 300
|
|
#define CLK_CHIPID 301
|
|
#define CLK_SYSREG 302
|
|
#define CLK_TZPC0 303
|
|
#define CLK_TZPC1 304
|
|
#define CLK_TZPC2 305
|
|
#define CLK_TZPC3 306
|
|
#define CLK_TZPC4 307
|
|
#define CLK_TZPC5 308
|
|
#define CLK_TZPC6 309
|
|
#define CLK_TZPC7 310
|
|
#define CLK_TZPC8 311
|
|
#define CLK_TZPC9 312
|
|
#define CLK_HDMI_CEC 313
|
|
#define CLK_SECKEY 314
|
|
#define CLK_MCT 315
|
|
#define CLK_WDT 316
|
|
#define CLK_RTC 317
|
|
#define CLK_TMU 318
|
|
#define CLK_TMU_GPU 319
|
|
#define CLK_PCLK66_GPIO 330
|
|
#define CLK_ACLK200_FSYS2 350
|
|
#define CLK_MMC0 351
|
|
#define CLK_MMC1 352
|
|
#define CLK_MMC2 353
|
|
#define CLK_SROMC 354
|
|
#define CLK_UFS 355
|
|
#define CLK_ACLK200_FSYS 360
|
|
#define CLK_TSI 361
|
|
#define CLK_PDMA0 362
|
|
#define CLK_PDMA1 363
|
|
#define CLK_RTIC 364
|
|
#define CLK_USBH20 365
|
|
#define CLK_USBD300 366
|
|
#define CLK_USBD301 367
|
|
#define CLK_ACLK400_MSCL 380
|
|
#define CLK_MSCL0 381
|
|
#define CLK_MSCL1 382
|
|
#define CLK_MSCL2 383
|
|
#define CLK_SMMU_MSCL0 384
|
|
#define CLK_SMMU_MSCL1 385
|
|
#define CLK_SMMU_MSCL2 386
|
|
#define CLK_ACLK333 400
|
|
#define CLK_MFC 401
|
|
#define CLK_SMMU_MFCL 402
|
|
#define CLK_SMMU_MFCR 403
|
|
#define CLK_ACLK200_DISP1 410
|
|
#define CLK_DSIM1 411
|
|
#define CLK_DP1 412
|
|
#define CLK_HDMI 413
|
|
#define CLK_ACLK300_DISP1 420
|
|
#define CLK_FIMD1 421
|
|
#define CLK_SMMU_FIMD1 422
|
|
#define CLK_ACLK166 430
|
|
#define CLK_MIXER 431
|
|
#define CLK_ACLK266 440
|
|
#define CLK_ROTATOR 441
|
|
#define CLK_MDMA1 442
|
|
#define CLK_SMMU_ROTATOR 443
|
|
#define CLK_SMMU_MDMA1 444
|
|
#define CLK_ACLK300_JPEG 450
|
|
#define CLK_JPEG 451
|
|
#define CLK_JPEG2 452
|
|
#define CLK_SMMU_JPEG 453
|
|
#define CLK_ACLK300_GSCL 460
|
|
#define CLK_SMMU_GSCL0 461
|
|
#define CLK_SMMU_GSCL1 462
|
|
#define CLK_GSCL_WA 463
|
|
#define CLK_GSCL_WB 464
|
|
#define CLK_GSCL0 465
|
|
#define CLK_GSCL1 466
|
|
#define CLK_CLK_3AA 467
|
|
#define CLK_ACLK266_G2D 470
|
|
#define CLK_SSS 471
|
|
#define CLK_SLIM_SSS 472
|
|
#define CLK_MDMA0 473
|
|
#define CLK_ACLK333_G2D 480
|
|
#define CLK_G2D 481
|
|
#define CLK_ACLK333_432_GSCL 490
|
|
#define CLK_SMMU_3AA 491
|
|
#define CLK_SMMU_FIMCL0 492
|
|
#define CLK_SMMU_FIMCL1 493
|
|
#define CLK_SMMU_FIMCL3 494
|
|
#define CLK_FIMC_LITE3 495
|
|
#define CLK_ACLK_G3D 500
|
|
#define CLK_G3D 501
|
|
#define CLK_SMMU_MIXER 502
|
|
|
|
/* mux clocks */
|
|
#define CLK_MOUT_HDMI 640
|
|
|
|
/* divider clocks */
|
|
#define CLK_DOUT_PIXEL 768
|
|
|
|
/* must be greater than maximal clock id */
|
|
#define CLK_NR_CLKS 769
|
|
|
|
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
|