Moshe Lazer 0ba422410b net/mlx5: Fix global UAR mapping ... Avoid double mapping of io mapped memory, Device page may be mapped to non-cached(NC) or to write-combining(WC). The code before this fix tries to map it both to WC and NC contrary to what stated in Intel's software developer manual. Here we remove the global WC mapping of all UARS "dev->priv.bf_mapping", since UAR mapping should be decided per UAR (e.g we want different mappings for EQs, CQs vs QPs). Caller will now have to choose whether to map via write-combining API or not. mlx5e SQs will choose write-combining in order to perform BlueFlame writes. Fixes: 88a85f99e5 ('TX latency optimization to save DMA reads') Signed-off-by: Moshe Lazer <moshel@mellanox.com> Reviewed-by: Achiad Shochat <achiad@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2016-03-01 17:28:00 -05:00
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mlx4	mlx4: Implement port type setting via devlink interface	2016-03-01 16:07:29 -05:00
mlx5/core	net/mlx5: Fix global UAR mapping	2016-03-01 17:28:00 -05:00
mlxsw	mlxsw: spectrum: Introduce port splitting	2016-03-01 16:07:31 -05:00
Kconfig	mlxsw: Introduce Mellanox switch driver core	2015-07-30 00:04:59 -07:00
Makefile	mlxsw: Introduce Mellanox switch driver core	2015-07-30 00:04:59 -07:00