mirror of https://gitee.com/openkylin/linux.git
662 lines
17 KiB
C
662 lines
17 KiB
C
/*
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* A driver for the CMOS camera controller in the Marvell 88ALP01 "cafe"
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* multifunction chip. Currently works with the Omnivision OV7670
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* sensor.
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*
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* The data sheet for this device can be found at:
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* http://www.marvell.com/products/pc_connectivity/88alp01/
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*
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* Copyright 2006-11 One Laptop Per Child Association, Inc.
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* Copyright 2006-11 Jonathan Corbet <corbet@lwn.net>
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*
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* Written by Jonathan Corbet, corbet@lwn.net.
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*
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* v4l2_device/v4l2_subdev conversion by:
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* Copyright (C) 2009 Hans Verkuil <hverkuil@xs4all.nl>
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*
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* This file may be distributed under the terms of the GNU General
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* Public License, version 2.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/videodev2.h>
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#include <media/v4l2-device.h>
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#include <linux/device.h>
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#include <linux/wait.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "mcam-core.h"
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#define CAFE_VERSION 0x000002
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/*
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* Parameters.
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*/
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MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
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MODULE_DESCRIPTION("Marvell 88ALP01 CMOS Camera Controller driver");
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MODULE_LICENSE("GPL");
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MODULE_SUPPORTED_DEVICE("Video");
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struct cafe_camera {
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int registered; /* Fully initialized? */
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struct mcam_camera mcam;
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struct pci_dev *pdev;
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wait_queue_head_t smbus_wait; /* Waiting on i2c events */
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};
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/*
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* Most of the camera controller registers are defined in mcam-core.h,
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* but the Cafe platform has some additional registers of its own;
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* they are described here.
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*/
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/*
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* "General purpose register" has a couple of GPIOs used for sensor
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* power and reset on OLPC XO 1.0 systems.
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*/
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#define REG_GPR 0xb4
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#define GPR_C1EN 0x00000020 /* Pad 1 (power down) enable */
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#define GPR_C0EN 0x00000010 /* Pad 0 (reset) enable */
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#define GPR_C1 0x00000002 /* Control 1 value */
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/*
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* Control 0 is wired to reset on OLPC machines. For ov7x sensors,
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* it is active low.
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*/
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#define GPR_C0 0x00000001 /* Control 0 value */
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/*
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* These registers control the SMBUS module for communicating
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* with the sensor.
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*/
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#define REG_TWSIC0 0xb8 /* TWSI (smbus) control 0 */
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#define TWSIC0_EN 0x00000001 /* TWSI enable */
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#define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
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#define TWSIC0_SID 0x000003fc /* Slave ID */
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/*
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* Subtle trickery: the slave ID field starts with bit 2. But the
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* Linux i2c stack wants to treat the bottommost bit as a separate
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* read/write bit, which is why slave ID's are usually presented
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* >>1. For consistency with that behavior, we shift over three
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* bits instead of two.
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*/
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#define TWSIC0_SID_SHIFT 3
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#define TWSIC0_CLKDIV 0x0007fc00 /* Clock divider */
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#define TWSIC0_MASKACK 0x00400000 /* Mask ack from sensor */
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#define TWSIC0_OVMAGIC 0x00800000 /* Make it work on OV sensors */
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#define REG_TWSIC1 0xbc /* TWSI control 1 */
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#define TWSIC1_DATA 0x0000ffff /* Data to/from camchip */
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#define TWSIC1_ADDR 0x00ff0000 /* Address (register) */
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#define TWSIC1_ADDR_SHIFT 16
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#define TWSIC1_READ 0x01000000 /* Set for read op */
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#define TWSIC1_WSTAT 0x02000000 /* Write status */
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#define TWSIC1_RVALID 0x04000000 /* Read data valid */
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#define TWSIC1_ERROR 0x08000000 /* Something screwed up */
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/*
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* Here's the weird global control registers
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*/
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#define REG_GL_CSR 0x3004 /* Control/status register */
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#define GCSR_SRS 0x00000001 /* SW Reset set */
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#define GCSR_SRC 0x00000002 /* SW Reset clear */
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#define GCSR_MRS 0x00000004 /* Master reset set */
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#define GCSR_MRC 0x00000008 /* HW Reset clear */
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#define GCSR_CCIC_EN 0x00004000 /* CCIC Clock enable */
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#define REG_GL_IMASK 0x300c /* Interrupt mask register */
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#define GIMSK_CCIC_EN 0x00000004 /* CCIC Interrupt enable */
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#define REG_GL_FCR 0x3038 /* GPIO functional control register */
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#define GFCR_GPIO_ON 0x08 /* Camera GPIO enabled */
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#define REG_GL_GPIOR 0x315c /* GPIO register */
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#define GGPIO_OUT 0x80000 /* GPIO output */
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#define GGPIO_VAL 0x00008 /* Output pin value */
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#define REG_LEN (REG_GL_IMASK + 4)
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/*
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* Debugging and related.
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*/
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#define cam_err(cam, fmt, arg...) \
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dev_err(&(cam)->pdev->dev, fmt, ##arg);
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#define cam_warn(cam, fmt, arg...) \
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dev_warn(&(cam)->pdev->dev, fmt, ##arg);
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/* -------------------------------------------------------------------- */
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/*
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* The I2C/SMBUS interface to the camera itself starts here. The
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* controller handles SMBUS itself, presenting a relatively simple register
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* interface; all we have to do is to tell it where to route the data.
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*/
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#define CAFE_SMBUS_TIMEOUT (HZ) /* generous */
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static inline struct cafe_camera *to_cam(struct v4l2_device *dev)
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{
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struct mcam_camera *m = container_of(dev, struct mcam_camera, v4l2_dev);
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return container_of(m, struct cafe_camera, mcam);
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}
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static int cafe_smbus_write_done(struct mcam_camera *mcam)
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{
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unsigned long flags;
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int c1;
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/*
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* We must delay after the interrupt, or the controller gets confused
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* and never does give us good status. Fortunately, we don't do this
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* often.
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*/
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udelay(20);
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spin_lock_irqsave(&mcam->dev_lock, flags);
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c1 = mcam_reg_read(mcam, REG_TWSIC1);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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return (c1 & (TWSIC1_WSTAT|TWSIC1_ERROR)) != TWSIC1_WSTAT;
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}
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static int cafe_smbus_write_data(struct cafe_camera *cam,
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u16 addr, u8 command, u8 value)
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{
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unsigned int rval;
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unsigned long flags;
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struct mcam_camera *mcam = &cam->mcam;
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spin_lock_irqsave(&mcam->dev_lock, flags);
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rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
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rval |= TWSIC0_OVMAGIC; /* Make OV sensors work */
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/*
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* Marvell sez set clkdiv to all 1's for now.
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*/
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rval |= TWSIC0_CLKDIV;
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mcam_reg_write(mcam, REG_TWSIC0, rval);
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(void) mcam_reg_read(mcam, REG_TWSIC1); /* force write */
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rval = value | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
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mcam_reg_write(mcam, REG_TWSIC1, rval);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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/* Unfortunately, reading TWSIC1 too soon after sending a command
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* causes the device to die.
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* Use a busy-wait because we often send a large quantity of small
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* commands at-once; using msleep() would cause a lot of context
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* switches which take longer than 2ms, resulting in a noticeable
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* boot-time and capture-start delays.
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*/
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mdelay(2);
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/*
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* Another sad fact is that sometimes, commands silently complete but
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* cafe_smbus_write_done() never becomes aware of this.
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* This happens at random and appears to possible occur with any
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* command.
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* We don't understand why this is. We work around this issue
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* with the timeout in the wait below, assuming that all commands
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* complete within the timeout.
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*/
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wait_event_timeout(cam->smbus_wait, cafe_smbus_write_done(mcam),
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CAFE_SMBUS_TIMEOUT);
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spin_lock_irqsave(&mcam->dev_lock, flags);
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rval = mcam_reg_read(mcam, REG_TWSIC1);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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if (rval & TWSIC1_WSTAT) {
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cam_err(cam, "SMBUS write (%02x/%02x/%02x) timed out\n", addr,
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command, value);
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return -EIO;
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}
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if (rval & TWSIC1_ERROR) {
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cam_err(cam, "SMBUS write (%02x/%02x/%02x) error\n", addr,
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command, value);
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return -EIO;
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}
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return 0;
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}
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static int cafe_smbus_read_done(struct mcam_camera *mcam)
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{
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unsigned long flags;
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int c1;
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/*
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* We must delay after the interrupt, or the controller gets confused
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* and never does give us good status. Fortunately, we don't do this
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* often.
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*/
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udelay(20);
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spin_lock_irqsave(&mcam->dev_lock, flags);
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c1 = mcam_reg_read(mcam, REG_TWSIC1);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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return c1 & (TWSIC1_RVALID|TWSIC1_ERROR);
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}
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static int cafe_smbus_read_data(struct cafe_camera *cam,
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u16 addr, u8 command, u8 *value)
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{
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unsigned int rval;
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unsigned long flags;
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struct mcam_camera *mcam = &cam->mcam;
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spin_lock_irqsave(&mcam->dev_lock, flags);
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rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
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rval |= TWSIC0_OVMAGIC; /* Make OV sensors work */
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/*
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* Marvel sez set clkdiv to all 1's for now.
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*/
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rval |= TWSIC0_CLKDIV;
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mcam_reg_write(mcam, REG_TWSIC0, rval);
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(void) mcam_reg_read(mcam, REG_TWSIC1); /* force write */
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rval = TWSIC1_READ | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
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mcam_reg_write(mcam, REG_TWSIC1, rval);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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wait_event_timeout(cam->smbus_wait,
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cafe_smbus_read_done(mcam), CAFE_SMBUS_TIMEOUT);
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spin_lock_irqsave(&mcam->dev_lock, flags);
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rval = mcam_reg_read(mcam, REG_TWSIC1);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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if (rval & TWSIC1_ERROR) {
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cam_err(cam, "SMBUS read (%02x/%02x) error\n", addr, command);
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return -EIO;
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}
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if (!(rval & TWSIC1_RVALID)) {
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cam_err(cam, "SMBUS read (%02x/%02x) timed out\n", addr,
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command);
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return -EIO;
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}
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*value = rval & 0xff;
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return 0;
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}
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/*
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* Perform a transfer over SMBUS. This thing is called under
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* the i2c bus lock, so we shouldn't race with ourselves...
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*/
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static int cafe_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
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unsigned short flags, char rw, u8 command,
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int size, union i2c_smbus_data *data)
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{
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struct cafe_camera *cam = i2c_get_adapdata(adapter);
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int ret = -EINVAL;
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/*
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* This interface would appear to only do byte data ops. OK
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* it can do word too, but the cam chip has no use for that.
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*/
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if (size != I2C_SMBUS_BYTE_DATA) {
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cam_err(cam, "funky xfer size %d\n", size);
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return -EINVAL;
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}
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if (rw == I2C_SMBUS_WRITE)
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ret = cafe_smbus_write_data(cam, addr, command, data->byte);
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else if (rw == I2C_SMBUS_READ)
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ret = cafe_smbus_read_data(cam, addr, command, &data->byte);
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return ret;
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}
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static void cafe_smbus_enable_irq(struct cafe_camera *cam)
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{
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unsigned long flags;
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spin_lock_irqsave(&cam->mcam.dev_lock, flags);
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mcam_reg_set_bit(&cam->mcam, REG_IRQMASK, TWSIIRQS);
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spin_unlock_irqrestore(&cam->mcam.dev_lock, flags);
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}
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static u32 cafe_smbus_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_SMBUS_READ_BYTE_DATA |
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I2C_FUNC_SMBUS_WRITE_BYTE_DATA;
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}
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static const struct i2c_algorithm cafe_smbus_algo = {
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.smbus_xfer = cafe_smbus_xfer,
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.functionality = cafe_smbus_func
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};
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static int cafe_smbus_setup(struct cafe_camera *cam)
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{
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struct i2c_adapter *adap;
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int ret;
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adap = kzalloc(sizeof(*adap), GFP_KERNEL);
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if (adap == NULL)
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return -ENOMEM;
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adap->owner = THIS_MODULE;
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adap->algo = &cafe_smbus_algo;
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strcpy(adap->name, "cafe_ccic");
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adap->dev.parent = &cam->pdev->dev;
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i2c_set_adapdata(adap, cam);
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ret = i2c_add_adapter(adap);
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if (ret) {
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printk(KERN_ERR "Unable to register cafe i2c adapter\n");
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kfree(adap);
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return ret;
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}
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cam->mcam.i2c_adapter = adap;
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cafe_smbus_enable_irq(cam);
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return 0;
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}
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static void cafe_smbus_shutdown(struct cafe_camera *cam)
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{
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i2c_del_adapter(cam->mcam.i2c_adapter);
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kfree(cam->mcam.i2c_adapter);
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}
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/*
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* Controller-level stuff
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*/
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static void cafe_ctlr_init(struct mcam_camera *mcam)
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{
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unsigned long flags;
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spin_lock_irqsave(&mcam->dev_lock, flags);
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/*
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* Added magic to bring up the hardware on the B-Test board
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*/
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mcam_reg_write(mcam, 0x3038, 0x8);
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mcam_reg_write(mcam, 0x315c, 0x80008);
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/*
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* Go through the dance needed to wake the device up.
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* Note that these registers are global and shared
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* with the NAND and SD devices. Interaction between the
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* three still needs to be examined.
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*/
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mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRS|GCSR_MRS); /* Needed? */
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mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRC|GCSR_MRC);
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mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRC|GCSR_MRS);
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/*
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* Here we must wait a bit for the controller to come around.
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*/
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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msleep(5);
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spin_lock_irqsave(&mcam->dev_lock, flags);
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mcam_reg_write(mcam, REG_GL_CSR, GCSR_CCIC_EN|GCSR_SRC|GCSR_MRC);
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mcam_reg_set_bit(mcam, REG_GL_IMASK, GIMSK_CCIC_EN);
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/*
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* Mask all interrupts.
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*/
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mcam_reg_write(mcam, REG_IRQMASK, 0);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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}
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static int cafe_ctlr_power_up(struct mcam_camera *mcam)
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{
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/*
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* Part one of the sensor dance: turn the global
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* GPIO signal on.
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*/
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mcam_reg_write(mcam, REG_GL_FCR, GFCR_GPIO_ON);
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mcam_reg_write(mcam, REG_GL_GPIOR, GGPIO_OUT|GGPIO_VAL);
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/*
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* Put the sensor into operational mode (assumes OLPC-style
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* wiring). Control 0 is reset - set to 1 to operate.
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* Control 1 is power down, set to 0 to operate.
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*/
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mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN); /* pwr up, reset */
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mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C0);
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return 0;
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}
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static void cafe_ctlr_power_down(struct mcam_camera *mcam)
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{
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mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C1);
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mcam_reg_write(mcam, REG_GL_FCR, GFCR_GPIO_ON);
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mcam_reg_write(mcam, REG_GL_GPIOR, GGPIO_OUT);
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}
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/*
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* The platform interrupt handler.
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*/
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static irqreturn_t cafe_irq(int irq, void *data)
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{
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struct cafe_camera *cam = data;
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struct mcam_camera *mcam = &cam->mcam;
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unsigned int irqs, handled;
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spin_lock(&mcam->dev_lock);
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irqs = mcam_reg_read(mcam, REG_IRQSTAT);
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handled = cam->registered && mccic_irq(mcam, irqs);
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if (irqs & TWSIIRQS) {
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mcam_reg_write(mcam, REG_IRQSTAT, TWSIIRQS);
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wake_up(&cam->smbus_wait);
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handled = 1;
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}
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spin_unlock(&mcam->dev_lock);
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return IRQ_RETVAL(handled);
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}
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/* -------------------------------------------------------------------------- */
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/*
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* PCI interface stuff.
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*/
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static int cafe_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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int ret;
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struct cafe_camera *cam;
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struct mcam_camera *mcam;
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/*
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* Start putting together one of our big camera structures.
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*/
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ret = -ENOMEM;
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cam = kzalloc(sizeof(struct cafe_camera), GFP_KERNEL);
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if (cam == NULL)
|
|
goto out;
|
|
cam->pdev = pdev;
|
|
mcam = &cam->mcam;
|
|
mcam->chip_id = MCAM_CAFE;
|
|
spin_lock_init(&mcam->dev_lock);
|
|
init_waitqueue_head(&cam->smbus_wait);
|
|
mcam->plat_power_up = cafe_ctlr_power_up;
|
|
mcam->plat_power_down = cafe_ctlr_power_down;
|
|
mcam->dev = &pdev->dev;
|
|
snprintf(mcam->bus_info, sizeof(mcam->bus_info), "PCI:%s", pci_name(pdev));
|
|
/*
|
|
* Set the clock speed for the XO 1; I don't believe this
|
|
* driver has ever run anywhere else.
|
|
*/
|
|
mcam->clock_speed = 45;
|
|
mcam->use_smbus = 1;
|
|
/*
|
|
* Vmalloc mode for buffers is traditional with this driver.
|
|
* We *might* be able to run DMA_contig, especially on a system
|
|
* with CMA in it.
|
|
*/
|
|
mcam->buffer_mode = B_vmalloc;
|
|
/*
|
|
* Get set up on the PCI bus.
|
|
*/
|
|
ret = pci_enable_device(pdev);
|
|
if (ret)
|
|
goto out_free;
|
|
pci_set_master(pdev);
|
|
|
|
ret = -EIO;
|
|
mcam->regs = pci_iomap(pdev, 0, 0);
|
|
if (!mcam->regs) {
|
|
printk(KERN_ERR "Unable to ioremap cafe-ccic regs\n");
|
|
goto out_disable;
|
|
}
|
|
mcam->regs_size = pci_resource_len(pdev, 0);
|
|
ret = request_irq(pdev->irq, cafe_irq, IRQF_SHARED, "cafe-ccic", cam);
|
|
if (ret)
|
|
goto out_iounmap;
|
|
|
|
/*
|
|
* Initialize the controller and leave it powered up. It will
|
|
* stay that way until the sensor driver shows up.
|
|
*/
|
|
cafe_ctlr_init(mcam);
|
|
cafe_ctlr_power_up(mcam);
|
|
/*
|
|
* Set up I2C/SMBUS communications. We have to drop the mutex here
|
|
* because the sensor could attach in this call chain, leading to
|
|
* unsightly deadlocks.
|
|
*/
|
|
ret = cafe_smbus_setup(cam);
|
|
if (ret)
|
|
goto out_pdown;
|
|
|
|
ret = mccic_register(mcam);
|
|
if (ret == 0) {
|
|
cam->registered = 1;
|
|
return 0;
|
|
}
|
|
|
|
cafe_smbus_shutdown(cam);
|
|
out_pdown:
|
|
cafe_ctlr_power_down(mcam);
|
|
free_irq(pdev->irq, cam);
|
|
out_iounmap:
|
|
pci_iounmap(pdev, mcam->regs);
|
|
out_disable:
|
|
pci_disable_device(pdev);
|
|
out_free:
|
|
kfree(cam);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
|
|
/*
|
|
* Shut down an initialized device
|
|
*/
|
|
static void cafe_shutdown(struct cafe_camera *cam)
|
|
{
|
|
mccic_shutdown(&cam->mcam);
|
|
cafe_smbus_shutdown(cam);
|
|
free_irq(cam->pdev->irq, cam);
|
|
pci_iounmap(cam->pdev, cam->mcam.regs);
|
|
}
|
|
|
|
|
|
static void cafe_pci_remove(struct pci_dev *pdev)
|
|
{
|
|
struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
|
|
struct cafe_camera *cam = to_cam(v4l2_dev);
|
|
|
|
if (cam == NULL) {
|
|
printk(KERN_WARNING "pci_remove on unknown pdev %p\n", pdev);
|
|
return;
|
|
}
|
|
cafe_shutdown(cam);
|
|
kfree(cam);
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
/*
|
|
* Basic power management.
|
|
*/
|
|
static int cafe_pci_suspend(struct pci_dev *pdev, pm_message_t state)
|
|
{
|
|
struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
|
|
struct cafe_camera *cam = to_cam(v4l2_dev);
|
|
int ret;
|
|
|
|
ret = pci_save_state(pdev);
|
|
if (ret)
|
|
return ret;
|
|
mccic_suspend(&cam->mcam);
|
|
pci_disable_device(pdev);
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int cafe_pci_resume(struct pci_dev *pdev)
|
|
{
|
|
struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
|
|
struct cafe_camera *cam = to_cam(v4l2_dev);
|
|
int ret = 0;
|
|
|
|
pci_restore_state(pdev);
|
|
ret = pci_enable_device(pdev);
|
|
|
|
if (ret) {
|
|
cam_warn(cam, "Unable to re-enable device on resume!\n");
|
|
return ret;
|
|
}
|
|
cafe_ctlr_init(&cam->mcam);
|
|
return mccic_resume(&cam->mcam);
|
|
}
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
static const struct pci_device_id cafe_ids[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL,
|
|
PCI_DEVICE_ID_MARVELL_88ALP01_CCIC) },
|
|
{ 0, }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, cafe_ids);
|
|
|
|
static struct pci_driver cafe_pci_driver = {
|
|
.name = "cafe1000-ccic",
|
|
.id_table = cafe_ids,
|
|
.probe = cafe_pci_probe,
|
|
.remove = cafe_pci_remove,
|
|
#ifdef CONFIG_PM
|
|
.suspend = cafe_pci_suspend,
|
|
.resume = cafe_pci_resume,
|
|
#endif
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init cafe_init(void)
|
|
{
|
|
int ret;
|
|
|
|
printk(KERN_NOTICE "Marvell M88ALP01 'CAFE' Camera Controller version %d\n",
|
|
CAFE_VERSION);
|
|
ret = pci_register_driver(&cafe_pci_driver);
|
|
if (ret) {
|
|
printk(KERN_ERR "Unable to register cafe_ccic driver\n");
|
|
goto out;
|
|
}
|
|
ret = 0;
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
|
|
static void __exit cafe_exit(void)
|
|
{
|
|
pci_unregister_driver(&cafe_pci_driver);
|
|
}
|
|
|
|
module_init(cafe_init);
|
|
module_exit(cafe_exit);
|