mirror of https://gitee.com/openkylin/linux.git
1040 lines
28 KiB
C
1040 lines
28 KiB
C
/* drivers/video/s1d13xxxfb.c
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*
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* (c) 2004 Simtec Electronics
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* (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
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* (c) 2009 Kristoffer Ericson <kristoffer.ericson@gmail.com>
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*
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* Driver for Epson S1D13xxx series framebuffer chips
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*
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* Adapted from
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* linux/drivers/video/skeletonfb.c
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* linux/drivers/video/epson1355fb.c
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* linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson)
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*
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* TODO: - handle dual screen display (CRT and LCD at the same time).
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* - check_var(), mode change, etc.
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* - probably not SMP safe :)
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* - support all bitblt operations on all cards
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/mm.h>
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#include <linux/mman.h>
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#include <linux/fb.h>
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#include <linux/spinlock_types.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <video/s1d13xxxfb.h>
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#define PFX "s1d13xxxfb: "
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#define BLIT "s1d13xxxfb_bitblt: "
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/*
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* set this to enable debugging on general functions
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*/
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#if 0
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#define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0)
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#else
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#define dbg(fmt, args...) do { } while (0)
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#endif
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/*
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* set this to enable debugging on 2D acceleration
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*/
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#if 0
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#define dbg_blit(fmt, args...) do { printk(KERN_INFO BLIT fmt, ## args); } while (0)
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#else
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#define dbg_blit(fmt, args...) do { } while (0)
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#endif
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/*
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* we make sure only one bitblt operation is running
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*/
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static DEFINE_SPINLOCK(s1d13xxxfb_bitblt_lock);
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/*
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* list of card production ids
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*/
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static const int s1d13xxxfb_prod_ids[] = {
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S1D13505_PROD_ID,
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S1D13506_PROD_ID,
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S1D13806_PROD_ID,
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};
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/*
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* List of card strings
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*/
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static const char *s1d13xxxfb_prod_names[] = {
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"S1D13505",
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"S1D13506",
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"S1D13806",
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};
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/*
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* here we define the default struct fb_fix_screeninfo
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*/
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static const struct fb_fix_screeninfo s1d13xxxfb_fix = {
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.id = S1D_FBID,
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.type = FB_TYPE_PACKED_PIXELS,
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.visual = FB_VISUAL_PSEUDOCOLOR,
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.xpanstep = 0,
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.ypanstep = 1,
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.ywrapstep = 0,
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.accel = FB_ACCEL_NONE,
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};
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static inline u8
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s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno)
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{
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#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
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regno=((regno & 1) ? (regno & ~1L) : (regno + 1));
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#endif
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return readb(par->regs + regno);
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}
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static inline void
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s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value)
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{
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#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
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regno=((regno & 1) ? (regno & ~1L) : (regno + 1));
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#endif
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writeb(value, par->regs + regno);
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}
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static inline void
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s1d13xxxfb_runinit(struct s1d13xxxfb_par *par,
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const struct s1d13xxxfb_regval *initregs,
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const unsigned int size)
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{
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int i;
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for (i = 0; i < size; i++) {
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if ((initregs[i].addr == S1DREG_DELAYOFF) ||
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(initregs[i].addr == S1DREG_DELAYON))
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mdelay((int)initregs[i].value);
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else {
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s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value);
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}
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}
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/* make sure the hardware can cope with us */
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mdelay(1);
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}
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static inline void
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lcd_enable(struct s1d13xxxfb_par *par, int enable)
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{
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u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
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if (enable)
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mode |= 0x01;
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else
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mode &= ~0x01;
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s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
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}
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static inline void
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crt_enable(struct s1d13xxxfb_par *par, int enable)
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{
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u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
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if (enable)
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mode |= 0x02;
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else
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mode &= ~0x02;
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s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
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}
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/*************************************************************
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framebuffer control functions
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*************************************************************/
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static inline void
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s1d13xxxfb_setup_pseudocolour(struct fb_info *info)
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{
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
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info->var.red.length = 4;
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info->var.green.length = 4;
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info->var.blue.length = 4;
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}
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static inline void
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s1d13xxxfb_setup_truecolour(struct fb_info *info)
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{
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info->fix.visual = FB_VISUAL_TRUECOLOR;
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info->var.bits_per_pixel = 16;
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info->var.red.length = 5;
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info->var.red.offset = 11;
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info->var.green.length = 6;
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info->var.green.offset = 5;
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info->var.blue.length = 5;
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info->var.blue.offset = 0;
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}
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/**
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* s1d13xxxfb_set_par - Alters the hardware state.
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* @info: frame buffer structure
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*
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* Using the fb_var_screeninfo in fb_info we set the depth of the
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* framebuffer. This function alters the par AND the
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* fb_fix_screeninfo stored in fb_info. It doesn't not alter var in
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* fb_info since we are using that data. This means we depend on the
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* data in var inside fb_info to be supported by the hardware.
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* xxxfb_check_var is always called before xxxfb_set_par to ensure this.
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*
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* XXX TODO: write proper s1d13xxxfb_check_var(), without which that
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* function is quite useless.
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*/
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static int
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s1d13xxxfb_set_par(struct fb_info *info)
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{
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struct s1d13xxxfb_par *s1dfb = info->par;
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unsigned int val;
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dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel);
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if ((s1dfb->display & 0x01)) /* LCD */
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val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE); /* read colour control */
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else /* CRT */
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val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE); /* read colour control */
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val &= ~0x07;
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switch (info->var.bits_per_pixel) {
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case 4:
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dbg("pseudo colour 4\n");
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s1d13xxxfb_setup_pseudocolour(info);
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val |= 2;
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break;
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case 8:
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dbg("pseudo colour 8\n");
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s1d13xxxfb_setup_pseudocolour(info);
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val |= 3;
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break;
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case 16:
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dbg("true colour\n");
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s1d13xxxfb_setup_truecolour(info);
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val |= 5;
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break;
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default:
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dbg("bpp not supported!\n");
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return -EINVAL;
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}
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dbg("writing %02x to display mode register\n", val);
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if ((s1dfb->display & 0x01)) /* LCD */
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s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val);
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else /* CRT */
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s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val);
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info->fix.line_length = info->var.xres * info->var.bits_per_pixel;
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info->fix.line_length /= 8;
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dbg("setting line_length to %d\n", info->fix.line_length);
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dbg("done setup\n");
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return 0;
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}
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/**
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* s1d13xxxfb_setcolreg - sets a color register.
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* @regno: Which register in the CLUT we are programming
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* @red: The red value which can be up to 16 bits wide
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* @green: The green value which can be up to 16 bits wide
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* @blue: The blue value which can be up to 16 bits wide.
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* @transp: If supported the alpha value which can be up to 16 bits wide.
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* @info: frame buffer info structure
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*
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* Returns negative errno on error, or zero on success.
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*/
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static int
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s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
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u_int transp, struct fb_info *info)
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{
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struct s1d13xxxfb_par *s1dfb = info->par;
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unsigned int pseudo_val;
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if (regno >= S1D_PALETTE_SIZE)
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return -EINVAL;
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dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n",
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regno, red, green, blue, transp);
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if (info->var.grayscale)
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red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16;
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switch (info->fix.visual) {
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case FB_VISUAL_TRUECOLOR:
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if (regno >= 16)
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return -EINVAL;
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/* deal with creating pseudo-palette entries */
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pseudo_val = (red >> 11) << info->var.red.offset;
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pseudo_val |= (green >> 10) << info->var.green.offset;
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pseudo_val |= (blue >> 11) << info->var.blue.offset;
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dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n",
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regno, pseudo_val);
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#if defined(CONFIG_PLAT_MAPPI)
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((u32 *)info->pseudo_palette)[regno] = cpu_to_le16(pseudo_val);
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#else
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((u32 *)info->pseudo_palette)[regno] = pseudo_val;
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#endif
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break;
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case FB_VISUAL_PSEUDOCOLOR:
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s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno);
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s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red);
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s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green);
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s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue);
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break;
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default:
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return -ENOSYS;
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}
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dbg("s1d13xxxfb_setcolreg: done\n");
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return 0;
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}
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/**
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* s1d13xxxfb_blank - blanks the display.
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* @blank_mode: the blank mode we want.
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* @info: frame buffer structure that represents a single frame buffer
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*
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* Blank the screen if blank_mode != 0, else unblank. Return 0 if
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* blanking succeeded, != 0 if un-/blanking failed due to e.g. a
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* video mode which doesn't support it. Implements VESA suspend
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* and powerdown modes on hardware that supports disabling hsync/vsync:
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* blank_mode == 2: suspend vsync
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* blank_mode == 3: suspend hsync
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* blank_mode == 4: powerdown
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*
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* Returns negative errno on error, or zero on success.
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*/
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static int
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s1d13xxxfb_blank(int blank_mode, struct fb_info *info)
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{
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struct s1d13xxxfb_par *par = info->par;
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dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info);
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switch (blank_mode) {
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case FB_BLANK_UNBLANK:
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case FB_BLANK_NORMAL:
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if ((par->display & 0x01) != 0)
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lcd_enable(par, 1);
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if ((par->display & 0x02) != 0)
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crt_enable(par, 1);
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break;
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case FB_BLANK_VSYNC_SUSPEND:
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case FB_BLANK_HSYNC_SUSPEND:
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break;
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case FB_BLANK_POWERDOWN:
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lcd_enable(par, 0);
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crt_enable(par, 0);
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break;
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default:
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return -EINVAL;
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}
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/* let fbcon do a soft blank for us */
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return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
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}
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/**
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* s1d13xxxfb_pan_display - Pans the display.
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* @var: frame buffer variable screen structure
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* @info: frame buffer structure that represents a single frame buffer
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*
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* Pan (or wrap, depending on the `vmode' field) the display using the
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* `yoffset' field of the `var' structure (`xoffset' not yet supported).
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* If the values don't fit, return -EINVAL.
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*
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* Returns negative errno on error, or zero on success.
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*/
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static int
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s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
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{
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struct s1d13xxxfb_par *par = info->par;
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u32 start;
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if (var->xoffset != 0) /* not yet ... */
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return -EINVAL;
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if (var->yoffset + info->var.yres > info->var.yres_virtual)
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return -EINVAL;
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start = (info->fix.line_length >> 1) * var->yoffset;
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if ((par->display & 0x01)) {
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/* LCD */
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s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff));
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s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff));
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s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f));
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} else {
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/* CRT */
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s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START0, (start & 0xff));
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s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START1, ((start >> 8) & 0xff));
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s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START2, ((start >> 16) & 0x0f));
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}
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return 0;
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}
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/************************************************************
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functions to handle bitblt acceleration
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************************************************************/
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/**
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* bltbit_wait_bitclear - waits for change in register value
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* @info : frambuffer structure
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* @bit : value currently in register
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* @timeout : ...
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*
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* waits until value changes FROM bit
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*
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*/
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static u8
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bltbit_wait_bitclear(struct fb_info *info, u8 bit, int timeout)
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{
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while (s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit) {
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udelay(10);
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if (!--timeout) {
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dbg_blit("wait_bitclear timeout\n");
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break;
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}
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}
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return timeout;
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}
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/*
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* s1d13xxxfb_bitblt_copyarea - accelerated copyarea function
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* @info : framebuffer structure
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* @area : fb_copyarea structure
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*
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* supports (atleast) S1D13506
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*
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*/
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static void
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s1d13xxxfb_bitblt_copyarea(struct fb_info *info, const struct fb_copyarea *area)
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{
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u32 dst, src;
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u32 stride;
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u16 reverse = 0;
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u16 sx = area->sx, sy = area->sy;
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u16 dx = area->dx, dy = area->dy;
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u16 width = area->width, height = area->height;
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u16 bpp;
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spin_lock(&s1d13xxxfb_bitblt_lock);
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/* bytes per xres line */
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bpp = (info->var.bits_per_pixel >> 3);
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stride = bpp * info->var.xres;
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/* reverse, calculate the last pixel in rectangle */
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if ((dy > sy) || ((dy == sy) && (dx >= sx))) {
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dst = (((dy + height - 1) * stride) + (bpp * (dx + width - 1)));
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src = (((sy + height - 1) * stride) + (bpp * (sx + width - 1)));
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reverse = 1;
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/* not reverse, calculate the first pixel in rectangle */
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} else { /* (y * xres) + (bpp * x) */
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dst = (dy * stride) + (bpp * dx);
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src = (sy * stride) + (bpp * sx);
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}
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/* set source address */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START0, (src & 0xff));
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START1, (src >> 8) & 0x00ff);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START2, (src >> 16) & 0x00ff);
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/* set destination address */
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dst & 0xff));
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, (dst >> 8) & 0x00ff);
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s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, (dst >> 16) & 0x00ff);
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/* program height and width */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, (width & 0xff) - 1);
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (width >> 8));
|
|
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, (height & 0xff) - 1);
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (height >> 8));
|
|
|
|
/* negative direction ROP */
|
|
if (reverse == 1) {
|
|
dbg_blit("(copyarea) negative rop\n");
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x03);
|
|
} else /* positive direction ROP */ {
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x02);
|
|
dbg_blit("(copyarea) positive rop\n");
|
|
}
|
|
|
|
/* set for rectangel mode and not linear */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
|
|
|
|
/* setup the bpp 1 = 16bpp, 0 = 8bpp*/
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (bpp >> 1));
|
|
|
|
/* set words per xres */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (stride >> 1) & 0xff);
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (stride >> 9));
|
|
|
|
dbg_blit("(copyarea) dx=%d, dy=%d\n", dx, dy);
|
|
dbg_blit("(copyarea) sx=%d, sy=%d\n", sx, sy);
|
|
dbg_blit("(copyarea) width=%d, height=%d\n", width - 1, height - 1);
|
|
dbg_blit("(copyarea) stride=%d\n", stride);
|
|
dbg_blit("(copyarea) bpp=%d=0x0%d, mem_offset1=%d, mem_offset2=%d\n", bpp, (bpp >> 1),
|
|
(stride >> 1) & 0xff, stride >> 9);
|
|
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CC_EXP, 0x0c);
|
|
|
|
/* initialize the engine */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
|
|
|
|
/* wait to complete */
|
|
bltbit_wait_bitclear(info, 0x80, 8000);
|
|
|
|
spin_unlock(&s1d13xxxfb_bitblt_lock);
|
|
}
|
|
|
|
/**
|
|
*
|
|
* s1d13xxxfb_bitblt_solidfill - accelerated solidfill function
|
|
* @info : framebuffer structure
|
|
* @rect : fb_fillrect structure
|
|
*
|
|
* supports (atleast 13506)
|
|
*
|
|
**/
|
|
static void
|
|
s1d13xxxfb_bitblt_solidfill(struct fb_info *info, const struct fb_fillrect *rect)
|
|
{
|
|
u32 screen_stride, dest;
|
|
u32 fg;
|
|
u16 bpp = (info->var.bits_per_pixel >> 3);
|
|
|
|
/* grab spinlock */
|
|
spin_lock(&s1d13xxxfb_bitblt_lock);
|
|
|
|
/* bytes per x width */
|
|
screen_stride = (bpp * info->var.xres);
|
|
|
|
/* bytes to starting point */
|
|
dest = ((rect->dy * screen_stride) + (bpp * rect->dx));
|
|
|
|
dbg_blit("(solidfill) dx=%d, dy=%d, stride=%d, dest=%d\n"
|
|
"(solidfill) : rect_width=%d, rect_height=%d\n",
|
|
rect->dx, rect->dy, screen_stride, dest,
|
|
rect->width - 1, rect->height - 1);
|
|
|
|
dbg_blit("(solidfill) : xres=%d, yres=%d, bpp=%d\n",
|
|
info->var.xres, info->var.yres,
|
|
info->var.bits_per_pixel);
|
|
dbg_blit("(solidfill) : rop=%d\n", rect->rop);
|
|
|
|
/* We split the destination into the three registers */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dest & 0x00ff));
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, ((dest >> 8) & 0x00ff));
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, ((dest >> 16) & 0x00ff));
|
|
|
|
/* give information regarding rectangel width */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, ((rect->width) & 0x00ff) - 1);
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (rect->width >> 8));
|
|
|
|
/* give information regarding rectangel height */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, ((rect->height) & 0x00ff) - 1);
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (rect->height >> 8));
|
|
|
|
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
|
|
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
|
|
fg = ((u32 *)info->pseudo_palette)[rect->color];
|
|
dbg_blit("(solidfill) truecolor/directcolor\n");
|
|
dbg_blit("(solidfill) pseudo_palette[%d] = %d\n", rect->color, fg);
|
|
} else {
|
|
fg = rect->color;
|
|
dbg_blit("(solidfill) color = %d\n", rect->color);
|
|
}
|
|
|
|
/* set foreground color */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC0, (fg & 0xff));
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC1, (fg >> 8) & 0xff);
|
|
|
|
/* set rectangual region of memory (rectangle and not linear) */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
|
|
|
|
/* set operation mode SOLID_FILL */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, BBLT_SOLID_FILL);
|
|
|
|
/* set bits per pixel (1 = 16bpp, 0 = 8bpp) */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (info->var.bits_per_pixel >> 4));
|
|
|
|
/* set the memory offset for the bblt in word sizes */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (screen_stride >> 1) & 0x00ff);
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (screen_stride >> 9));
|
|
|
|
/* and away we go.... */
|
|
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
|
|
|
|
/* wait until its done */
|
|
bltbit_wait_bitclear(info, 0x80, 8000);
|
|
|
|
/* let others play */
|
|
spin_unlock(&s1d13xxxfb_bitblt_lock);
|
|
}
|
|
|
|
/* framebuffer information structures */
|
|
static struct fb_ops s1d13xxxfb_fbops = {
|
|
.owner = THIS_MODULE,
|
|
.fb_set_par = s1d13xxxfb_set_par,
|
|
.fb_setcolreg = s1d13xxxfb_setcolreg,
|
|
.fb_blank = s1d13xxxfb_blank,
|
|
|
|
.fb_pan_display = s1d13xxxfb_pan_display,
|
|
|
|
/* gets replaced at chip detection time */
|
|
.fb_fillrect = cfb_fillrect,
|
|
.fb_copyarea = cfb_copyarea,
|
|
.fb_imageblit = cfb_imageblit,
|
|
};
|
|
|
|
static int s1d13xxxfb_width_tab[2][4] = {
|
|
{4, 8, 16, -1},
|
|
{9, 12, 18, -1},
|
|
};
|
|
|
|
/**
|
|
* s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
|
|
* hardware setup.
|
|
* @info: frame buffer structure
|
|
*
|
|
* We setup the framebuffer structures according to the current
|
|
* hardware setup. On some machines, the BIOS will have filled
|
|
* the chip registers with such info, on others, these values will
|
|
* have been written in some init procedure. In any case, the
|
|
* software values needs to match the hardware ones. This is what
|
|
* this function ensures.
|
|
*
|
|
* Note: some of the hardcoded values here might need some love to
|
|
* work on various chips, and might need to no longer be hardcoded.
|
|
*/
|
|
static void s1d13xxxfb_fetch_hw_state(struct fb_info *info)
|
|
{
|
|
struct fb_var_screeninfo *var = &info->var;
|
|
struct fb_fix_screeninfo *fix = &info->fix;
|
|
struct s1d13xxxfb_par *par = info->par;
|
|
u8 panel, display;
|
|
u16 offset;
|
|
u32 xres, yres;
|
|
u32 xres_virtual, yres_virtual;
|
|
int bpp, lcd_bpp;
|
|
int is_color, is_dual, is_tft;
|
|
int lcd_enabled, crt_enabled;
|
|
|
|
fix->type = FB_TYPE_PACKED_PIXELS;
|
|
|
|
/* general info */
|
|
par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
|
|
crt_enabled = (par->display & 0x02) != 0;
|
|
lcd_enabled = (par->display & 0x01) != 0;
|
|
|
|
if (lcd_enabled && crt_enabled)
|
|
printk(KERN_WARNING PFX "Warning: LCD and CRT detected, using LCD\n");
|
|
|
|
if (lcd_enabled)
|
|
display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE);
|
|
else /* CRT */
|
|
display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE);
|
|
|
|
bpp = display & 0x07;
|
|
|
|
switch (bpp) {
|
|
case 2: /* 4 bpp */
|
|
case 3: /* 8 bpp */
|
|
var->bits_per_pixel = 8;
|
|
var->red.offset = var->green.offset = var->blue.offset = 0;
|
|
var->red.length = var->green.length = var->blue.length = 8;
|
|
break;
|
|
case 5: /* 16 bpp */
|
|
s1d13xxxfb_setup_truecolour(info);
|
|
break;
|
|
default:
|
|
dbg("bpp: %i\n", bpp);
|
|
}
|
|
fb_alloc_cmap(&info->cmap, 256, 0);
|
|
|
|
/* LCD info */
|
|
panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE);
|
|
is_color = (panel & 0x04) != 0;
|
|
is_dual = (panel & 0x02) != 0;
|
|
is_tft = (panel & 0x01) != 0;
|
|
lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3];
|
|
|
|
if (lcd_enabled) {
|
|
xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8;
|
|
yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) +
|
|
((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1);
|
|
|
|
offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) +
|
|
((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8));
|
|
} else { /* crt */
|
|
xres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_HWIDTH) + 1) * 8;
|
|
yres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT0) +
|
|
((s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT1) & 0x03) << 8) + 1);
|
|
|
|
offset = (s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF0) +
|
|
((s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF1) & 0x7) << 8));
|
|
}
|
|
xres_virtual = offset * 16 / var->bits_per_pixel;
|
|
yres_virtual = fix->smem_len / (offset * 2);
|
|
|
|
var->xres = xres;
|
|
var->yres = yres;
|
|
var->xres_virtual = xres_virtual;
|
|
var->yres_virtual = yres_virtual;
|
|
var->xoffset = var->yoffset = 0;
|
|
|
|
fix->line_length = offset * 2;
|
|
|
|
var->grayscale = !is_color;
|
|
|
|
var->activate = FB_ACTIVATE_NOW;
|
|
|
|
dbg(PFX "bpp=%d, lcd_bpp=%d, "
|
|
"crt_enabled=%d, lcd_enabled=%d\n",
|
|
var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled);
|
|
dbg(PFX "xres=%d, yres=%d, vxres=%d, vyres=%d "
|
|
"is_color=%d, is_dual=%d, is_tft=%d\n",
|
|
xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft);
|
|
}
|
|
|
|
|
|
static int
|
|
s1d13xxxfb_remove(struct platform_device *pdev)
|
|
{
|
|
struct fb_info *info = platform_get_drvdata(pdev);
|
|
struct s1d13xxxfb_par *par = NULL;
|
|
|
|
if (info) {
|
|
par = info->par;
|
|
if (par && par->regs) {
|
|
/* disable output & enable powersave */
|
|
s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00);
|
|
s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11);
|
|
iounmap(par->regs);
|
|
}
|
|
|
|
fb_dealloc_cmap(&info->cmap);
|
|
|
|
if (info->screen_base)
|
|
iounmap(info->screen_base);
|
|
|
|
framebuffer_release(info);
|
|
}
|
|
|
|
release_mem_region(pdev->resource[0].start,
|
|
pdev->resource[0].end - pdev->resource[0].start +1);
|
|
release_mem_region(pdev->resource[1].start,
|
|
pdev->resource[1].end - pdev->resource[1].start +1);
|
|
return 0;
|
|
}
|
|
|
|
static int s1d13xxxfb_probe(struct platform_device *pdev)
|
|
{
|
|
struct s1d13xxxfb_par *default_par;
|
|
struct fb_info *info;
|
|
struct s1d13xxxfb_pdata *pdata = NULL;
|
|
int ret = 0;
|
|
int i;
|
|
u8 revision, prod_id;
|
|
|
|
dbg("probe called: device is %p\n", pdev);
|
|
|
|
printk(KERN_INFO "Epson S1D13XXX FB Driver\n");
|
|
|
|
/* enable platform-dependent hardware glue, if any */
|
|
if (dev_get_platdata(&pdev->dev))
|
|
pdata = dev_get_platdata(&pdev->dev);
|
|
|
|
if (pdata && pdata->platform_init_video)
|
|
pdata->platform_init_video();
|
|
|
|
if (pdev->num_resources != 2) {
|
|
dev_err(&pdev->dev, "invalid num_resources: %i\n",
|
|
pdev->num_resources);
|
|
ret = -ENODEV;
|
|
goto bail;
|
|
}
|
|
|
|
/* resource[0] is VRAM, resource[1] is registers */
|
|
if (pdev->resource[0].flags != IORESOURCE_MEM
|
|
|| pdev->resource[1].flags != IORESOURCE_MEM) {
|
|
dev_err(&pdev->dev, "invalid resource type\n");
|
|
ret = -ENODEV;
|
|
goto bail;
|
|
}
|
|
|
|
if (!request_mem_region(pdev->resource[0].start,
|
|
pdev->resource[0].end - pdev->resource[0].start +1, "s1d13xxxfb mem")) {
|
|
dev_dbg(&pdev->dev, "request_mem_region failed\n");
|
|
ret = -EBUSY;
|
|
goto bail;
|
|
}
|
|
|
|
if (!request_mem_region(pdev->resource[1].start,
|
|
pdev->resource[1].end - pdev->resource[1].start +1, "s1d13xxxfb regs")) {
|
|
dev_dbg(&pdev->dev, "request_mem_region failed\n");
|
|
ret = -EBUSY;
|
|
goto bail;
|
|
}
|
|
|
|
info = framebuffer_alloc(sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev);
|
|
if (!info) {
|
|
ret = -ENOMEM;
|
|
goto bail;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, info);
|
|
default_par = info->par;
|
|
default_par->regs = ioremap_nocache(pdev->resource[1].start,
|
|
pdev->resource[1].end - pdev->resource[1].start +1);
|
|
if (!default_par->regs) {
|
|
printk(KERN_ERR PFX "unable to map registers\n");
|
|
ret = -ENOMEM;
|
|
goto bail;
|
|
}
|
|
info->pseudo_palette = default_par->pseudo_palette;
|
|
|
|
info->screen_base = ioremap_nocache(pdev->resource[0].start,
|
|
pdev->resource[0].end - pdev->resource[0].start +1);
|
|
|
|
if (!info->screen_base) {
|
|
printk(KERN_ERR PFX "unable to map framebuffer\n");
|
|
ret = -ENOMEM;
|
|
goto bail;
|
|
}
|
|
|
|
/* production id is top 6 bits */
|
|
prod_id = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) >> 2;
|
|
/* revision id is lower 2 bits */
|
|
revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) & 0x3;
|
|
ret = -ENODEV;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s1d13xxxfb_prod_ids); i++) {
|
|
if (prod_id == s1d13xxxfb_prod_ids[i]) {
|
|
/* looks like we got it in our list */
|
|
default_par->prod_id = prod_id;
|
|
default_par->revision = revision;
|
|
ret = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!ret) {
|
|
printk(KERN_INFO PFX "chip production id %i = %s\n",
|
|
prod_id, s1d13xxxfb_prod_names[i]);
|
|
printk(KERN_INFO PFX "chip revision %i\n", revision);
|
|
} else {
|
|
printk(KERN_INFO PFX
|
|
"unknown chip production id %i, revision %i\n",
|
|
prod_id, revision);
|
|
printk(KERN_INFO PFX "please contact maintainer\n");
|
|
goto bail;
|
|
}
|
|
|
|
info->fix = s1d13xxxfb_fix;
|
|
info->fix.mmio_start = pdev->resource[1].start;
|
|
info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start + 1;
|
|
info->fix.smem_start = pdev->resource[0].start;
|
|
info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start + 1;
|
|
|
|
printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
|
|
default_par->regs, info->fix.smem_len / 1024, info->screen_base);
|
|
|
|
info->par = default_par;
|
|
info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
|
|
info->fbops = &s1d13xxxfb_fbops;
|
|
|
|
switch(prod_id) {
|
|
case S1D13506_PROD_ID: /* activate acceleration */
|
|
s1d13xxxfb_fbops.fb_fillrect = s1d13xxxfb_bitblt_solidfill;
|
|
s1d13xxxfb_fbops.fb_copyarea = s1d13xxxfb_bitblt_copyarea;
|
|
info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
|
|
FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* perform "manual" chip initialization, if needed */
|
|
if (pdata && pdata->initregs)
|
|
s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize);
|
|
|
|
s1d13xxxfb_fetch_hw_state(info);
|
|
|
|
if (register_framebuffer(info) < 0) {
|
|
ret = -EINVAL;
|
|
goto bail;
|
|
}
|
|
|
|
fb_info(info, "%s frame buffer device\n", info->fix.id);
|
|
|
|
return 0;
|
|
|
|
bail:
|
|
s1d13xxxfb_remove(pdev);
|
|
return ret;
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct fb_info *info = platform_get_drvdata(dev);
|
|
struct s1d13xxxfb_par *s1dfb = info->par;
|
|
struct s1d13xxxfb_pdata *pdata = NULL;
|
|
|
|
/* disable display */
|
|
lcd_enable(s1dfb, 0);
|
|
crt_enable(s1dfb, 0);
|
|
|
|
if (dev_get_platdata(&dev->dev))
|
|
pdata = dev_get_platdata(&dev->dev);
|
|
|
|
#if 0
|
|
if (!s1dfb->disp_save)
|
|
s1dfb->disp_save = kmalloc(info->fix.smem_len, GFP_KERNEL);
|
|
|
|
if (!s1dfb->disp_save) {
|
|
printk(KERN_ERR PFX "no memory to save screen\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
memcpy_fromio(s1dfb->disp_save, info->screen_base, info->fix.smem_len);
|
|
#else
|
|
s1dfb->disp_save = NULL;
|
|
#endif
|
|
|
|
if (!s1dfb->regs_save)
|
|
s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL);
|
|
|
|
if (!s1dfb->regs_save) {
|
|
printk(KERN_ERR PFX "no memory to save registers");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* backup all registers */
|
|
memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len);
|
|
|
|
/* now activate power save mode */
|
|
s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11);
|
|
|
|
if (pdata && pdata->platform_suspend_video)
|
|
return pdata->platform_suspend_video();
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
static int s1d13xxxfb_resume(struct platform_device *dev)
|
|
{
|
|
struct fb_info *info = platform_get_drvdata(dev);
|
|
struct s1d13xxxfb_par *s1dfb = info->par;
|
|
struct s1d13xxxfb_pdata *pdata = NULL;
|
|
|
|
/* awaken the chip */
|
|
s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10);
|
|
|
|
/* do not let go until SDRAM "wakes up" */
|
|
while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01))
|
|
udelay(10);
|
|
|
|
if (dev_get_platdata(&dev->dev))
|
|
pdata = dev_get_platdata(&dev->dev);
|
|
|
|
if (s1dfb->regs_save) {
|
|
/* will write RO regs, *should* get away with it :) */
|
|
memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len);
|
|
kfree(s1dfb->regs_save);
|
|
}
|
|
|
|
if (s1dfb->disp_save) {
|
|
memcpy_toio(info->screen_base, s1dfb->disp_save,
|
|
info->fix.smem_len);
|
|
kfree(s1dfb->disp_save); /* XXX kmalloc()'d when? */
|
|
}
|
|
|
|
if ((s1dfb->display & 0x01) != 0)
|
|
lcd_enable(s1dfb, 1);
|
|
if ((s1dfb->display & 0x02) != 0)
|
|
crt_enable(s1dfb, 1);
|
|
|
|
if (pdata && pdata->platform_resume_video)
|
|
return pdata->platform_resume_video();
|
|
else
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM */
|
|
|
|
static struct platform_driver s1d13xxxfb_driver = {
|
|
.probe = s1d13xxxfb_probe,
|
|
.remove = s1d13xxxfb_remove,
|
|
#ifdef CONFIG_PM
|
|
.suspend = s1d13xxxfb_suspend,
|
|
.resume = s1d13xxxfb_resume,
|
|
#endif
|
|
.driver = {
|
|
.name = S1D_DEVICENAME,
|
|
},
|
|
};
|
|
|
|
|
|
static int __init
|
|
s1d13xxxfb_init(void)
|
|
{
|
|
|
|
#ifndef MODULE
|
|
if (fb_get_options("s1d13xxxfb", NULL))
|
|
return -ENODEV;
|
|
#endif
|
|
|
|
return platform_driver_register(&s1d13xxxfb_driver);
|
|
}
|
|
|
|
|
|
static void __exit
|
|
s1d13xxxfb_exit(void)
|
|
{
|
|
platform_driver_unregister(&s1d13xxxfb_driver);
|
|
}
|
|
|
|
module_init(s1d13xxxfb_init);
|
|
module_exit(s1d13xxxfb_exit);
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices");
|
|
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Thibaut VARENE <varenet@parisc-linux.org>");
|