mirror of https://gitee.com/openkylin/linux.git
514 lines
16 KiB
C
514 lines
16 KiB
C
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MIPS_ASM_MIPS_CM_H__
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#define __MIPS_ASM_MIPS_CM_H__
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/types.h>
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/* The base address of the CM GCR block */
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extern void __iomem *mips_cm_base;
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/* The base address of the CM L2-only sync region */
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extern void __iomem *mips_cm_l2sync_base;
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/**
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* __mips_cm_phys_base - retrieve the physical base address of the CM
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*
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* This function returns the physical base address of the Coherence Manager
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* global control block, or 0 if no Coherence Manager is present. It provides
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* a default implementation which reads the CMGCRBase register where available,
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* and may be overriden by platforms which determine this address in a
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* different way by defining a function with the same prototype except for the
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* name mips_cm_phys_base (without underscores).
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*/
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extern phys_addr_t __mips_cm_phys_base(void);
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/*
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* mips_cm_is64 - determine CM register width
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*
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* The CM register width is determined by the version of the CM, with CM3
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* introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
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* However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
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* or vice-versa. This variable indicates the width of the memory accesses
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* that the kernel will perform to GCRs, which may differ from the actual
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* width of the GCRs.
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*
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* It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
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*/
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extern int mips_cm_is64;
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/**
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* mips_cm_error_report - Report CM cache errors
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*/
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#ifdef CONFIG_MIPS_CM
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extern void mips_cm_error_report(void);
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#else
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static inline void mips_cm_error_report(void) {}
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#endif
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/**
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* mips_cm_probe - probe for a Coherence Manager
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*
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* Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
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* is successfully detected, else -errno.
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*/
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#ifdef CONFIG_MIPS_CM
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extern int mips_cm_probe(void);
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#else
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static inline int mips_cm_probe(void)
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{
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return -ENODEV;
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}
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#endif
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/**
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* mips_cm_present - determine whether a Coherence Manager is present
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*
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* Returns true if a CM is present in the system, else false.
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*/
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static inline bool mips_cm_present(void)
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{
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#ifdef CONFIG_MIPS_CM
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return mips_cm_base != NULL;
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#else
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return false;
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#endif
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}
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/**
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* mips_cm_has_l2sync - determine whether an L2-only sync region is present
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*
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* Returns true if the system implements an L2-only sync region, else false.
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*/
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static inline bool mips_cm_has_l2sync(void)
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{
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#ifdef CONFIG_MIPS_CM
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return mips_cm_l2sync_base != NULL;
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#else
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return false;
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#endif
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}
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/* Offsets to register blocks from the CM base address */
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#define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */
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#define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */
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#define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */
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#define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */
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/* Total size of the CM memory mapped registers */
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#define MIPS_CM_GCR_SIZE 0x8000
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/* Size of the L2-only sync region */
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#define MIPS_CM_L2SYNC_SIZE 0x1000
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/* Macros to ease the creation of register access functions */
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#define BUILD_CM_R_(name, off) \
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static inline unsigned long __iomem *addr_gcr_##name(void) \
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{ \
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return (unsigned long __iomem *)(mips_cm_base + (off)); \
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} \
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\
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static inline u32 read32_gcr_##name(void) \
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{ \
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return __raw_readl(addr_gcr_##name()); \
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} \
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\
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static inline u64 read64_gcr_##name(void) \
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{ \
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void __iomem *addr = addr_gcr_##name(); \
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u64 ret; \
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\
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if (mips_cm_is64) { \
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ret = __raw_readq(addr); \
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} else { \
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ret = __raw_readl(addr); \
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ret |= (u64)__raw_readl(addr + 0x4) << 32; \
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} \
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\
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return ret; \
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} \
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\
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static inline unsigned long read_gcr_##name(void) \
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{ \
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if (mips_cm_is64) \
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return read64_gcr_##name(); \
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else \
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return read32_gcr_##name(); \
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}
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#define BUILD_CM__W(name, off) \
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static inline void write32_gcr_##name(u32 value) \
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{ \
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__raw_writel(value, addr_gcr_##name()); \
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} \
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\
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static inline void write64_gcr_##name(u64 value) \
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{ \
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__raw_writeq(value, addr_gcr_##name()); \
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} \
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\
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static inline void write_gcr_##name(unsigned long value) \
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{ \
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if (mips_cm_is64) \
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write64_gcr_##name(value); \
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else \
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write32_gcr_##name(value); \
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}
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#define BUILD_CM_RW(name, off) \
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BUILD_CM_R_(name, off) \
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BUILD_CM__W(name, off)
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#define BUILD_CM_Cx_R_(name, off) \
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BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off)) \
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BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off))
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#define BUILD_CM_Cx__W(name, off) \
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BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off)) \
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BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off))
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#define BUILD_CM_Cx_RW(name, off) \
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BUILD_CM_Cx_R_(name, off) \
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BUILD_CM_Cx__W(name, off)
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/* GCB register accessor functions */
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BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00)
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BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08)
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BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20)
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BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30)
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BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40)
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BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48)
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BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50)
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BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58)
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BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70)
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BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80)
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BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88)
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BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90)
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BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98)
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BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0)
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BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8)
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BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0)
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BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8)
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BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0)
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BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8)
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BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0)
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BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0)
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BUILD_CM_RW(l2_config, MIPS_CM_GCB_OFS + 0x130)
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BUILD_CM_RW(sys_config2, MIPS_CM_GCB_OFS + 0x150)
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BUILD_CM_RW(l2_pft_control, MIPS_CM_GCB_OFS + 0x300)
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BUILD_CM_RW(l2_pft_control_b, MIPS_CM_GCB_OFS + 0x308)
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/* Core Local & Core Other register accessor functions */
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BUILD_CM_Cx_RW(reset_release, 0x00)
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BUILD_CM_Cx_RW(coherence, 0x08)
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BUILD_CM_Cx_R_(config, 0x10)
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BUILD_CM_Cx_RW(other, 0x18)
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BUILD_CM_Cx_RW(reset_base, 0x20)
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BUILD_CM_Cx_R_(id, 0x28)
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BUILD_CM_Cx_RW(reset_ext_base, 0x30)
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BUILD_CM_Cx_R_(tcid_0_priority, 0x40)
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BUILD_CM_Cx_R_(tcid_1_priority, 0x48)
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BUILD_CM_Cx_R_(tcid_2_priority, 0x50)
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BUILD_CM_Cx_R_(tcid_3_priority, 0x58)
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BUILD_CM_Cx_R_(tcid_4_priority, 0x60)
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BUILD_CM_Cx_R_(tcid_5_priority, 0x68)
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BUILD_CM_Cx_R_(tcid_6_priority, 0x70)
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BUILD_CM_Cx_R_(tcid_7_priority, 0x78)
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BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
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/* GCR_CONFIG register fields */
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#define CM_GCR_CONFIG_NUMIOCU_SHF 8
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#define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8)
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#define CM_GCR_CONFIG_PCORES_SHF 0
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#define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0)
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/* GCR_BASE register fields */
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#define CM_GCR_BASE_GCRBASE_SHF 15
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#define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15)
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#define CM_GCR_BASE_CMDEFTGT_SHF 0
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#define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0)
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#define CM_GCR_BASE_CMDEFTGT_DISABLED 0
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#define CM_GCR_BASE_CMDEFTGT_MEM 1
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#define CM_GCR_BASE_CMDEFTGT_IOCU0 2
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#define CM_GCR_BASE_CMDEFTGT_IOCU1 3
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/* GCR_RESET_EXT_BASE register fields */
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#define CM_GCR_RESET_EXT_BASE_EVARESET BIT(31)
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#define CM_GCR_RESET_EXT_BASE_UEB BIT(30)
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/* GCR_ACCESS register fields */
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#define CM_GCR_ACCESS_ACCESSEN_SHF 0
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#define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0)
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/* GCR_REV register fields */
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#define CM_GCR_REV_MAJOR_SHF 8
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#define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8)
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#define CM_GCR_REV_MINOR_SHF 0
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#define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0)
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#define CM_ENCODE_REV(major, minor) \
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(((major) << CM_GCR_REV_MAJOR_SHF) | \
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((minor) << CM_GCR_REV_MINOR_SHF))
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#define CM_REV_CM2 CM_ENCODE_REV(6, 0)
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#define CM_REV_CM2_5 CM_ENCODE_REV(7, 0)
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#define CM_REV_CM3 CM_ENCODE_REV(8, 0)
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/* GCR_ERROR_CAUSE register fields */
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#define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27
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#define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27)
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#define CM3_GCR_ERROR_CAUSE_ERRTYPE_SHF 58
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#define CM3_GCR_ERROR_CAUSE_ERRTYPE_MSK GENMASK_ULL(63, 58)
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#define CM_GCR_ERROR_CAUSE_ERRINFO_SHF 0
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#define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0)
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/* GCR_ERROR_MULT register fields */
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#define CM_GCR_ERROR_MULT_ERR2ND_SHF 0
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#define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0)
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/* GCR_L2_ONLY_SYNC_BASE register fields */
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#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF 12
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#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12)
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#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF 0
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#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0)
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/* GCR_GIC_BASE register fields */
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#define CM_GCR_GIC_BASE_GICBASE_SHF 17
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#define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17)
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#define CM_GCR_GIC_BASE_GICEN_SHF 0
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#define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0)
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/* GCR_CPC_BASE register fields */
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#define CM_GCR_CPC_BASE_CPCBASE_SHF 17
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#define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17)
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#define CM_GCR_CPC_BASE_CPCEN_SHF 0
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#define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0)
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/* GCR_GIC_STATUS register fields */
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#define CM_GCR_GIC_STATUS_GICEX_SHF 0
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#define CM_GCR_GIC_STATUS_GICEX_MSK (_ULCAST_(0x1) << 0)
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/* GCR_REGn_BASE register fields */
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#define CM_GCR_REGn_BASE_BASEADDR_SHF 16
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#define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16)
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/* GCR_REGn_MASK register fields */
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#define CM_GCR_REGn_MASK_ADDRMASK_SHF 16
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#define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16)
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#define CM_GCR_REGn_MASK_CCAOVR_SHF 5
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#define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5)
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#define CM_GCR_REGn_MASK_CCAOVREN_SHF 4
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#define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4)
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#define CM_GCR_REGn_MASK_DROPL2_SHF 2
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#define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2)
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#define CM_GCR_REGn_MASK_CMTGT_SHF 0
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#define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0)
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#define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0)
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#define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0)
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#define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0)
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#define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0)
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/* GCR_GIC_STATUS register fields */
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#define CM_GCR_GIC_STATUS_EX_SHF 0
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#define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
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/* GCR_CPC_STATUS register fields */
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#define CM_GCR_CPC_STATUS_EX_SHF 0
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#define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
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/* GCR_L2_CONFIG register fields */
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#define CM_GCR_L2_CONFIG_BYPASS_SHF 20
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#define CM_GCR_L2_CONFIG_BYPASS_MSK (_ULCAST_(0x1) << 20)
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#define CM_GCR_L2_CONFIG_SET_SIZE_SHF 12
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#define CM_GCR_L2_CONFIG_SET_SIZE_MSK (_ULCAST_(0xf) << 12)
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#define CM_GCR_L2_CONFIG_LINE_SIZE_SHF 8
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#define CM_GCR_L2_CONFIG_LINE_SIZE_MSK (_ULCAST_(0xf) << 8)
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#define CM_GCR_L2_CONFIG_ASSOC_SHF 0
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#define CM_GCR_L2_CONFIG_ASSOC_MSK (_ULCAST_(0xff) << 0)
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/* GCR_SYS_CONFIG2 register fields */
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#define CM_GCR_SYS_CONFIG2_MAXVPW_SHF 0
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#define CM_GCR_SYS_CONFIG2_MAXVPW_MSK (_ULCAST_(0xf) << 0)
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/* GCR_L2_PFT_CONTROL register fields */
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#define CM_GCR_L2_PFT_CONTROL_PAGEMASK_SHF 12
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#define CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK (_ULCAST_(0xfffff) << 12)
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#define CM_GCR_L2_PFT_CONTROL_PFTEN_SHF 8
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#define CM_GCR_L2_PFT_CONTROL_PFTEN_MSK (_ULCAST_(0x1) << 8)
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#define CM_GCR_L2_PFT_CONTROL_NPFT_SHF 0
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#define CM_GCR_L2_PFT_CONTROL_NPFT_MSK (_ULCAST_(0xff) << 0)
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/* GCR_L2_PFT_CONTROL_B register fields */
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#define CM_GCR_L2_PFT_CONTROL_B_CEN_SHF 8
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#define CM_GCR_L2_PFT_CONTROL_B_CEN_MSK (_ULCAST_(0x1) << 8)
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#define CM_GCR_L2_PFT_CONTROL_B_PORTID_SHF 0
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#define CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK (_ULCAST_(0xff) << 0)
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/* GCR_Cx_COHERENCE register fields */
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#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0
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#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0)
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/* GCR_Cx_CONFIG register fields */
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#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10
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#define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10)
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#define CM_GCR_Cx_CONFIG_PVPE_SHF 0
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#define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x3ff) << 0)
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/* GCR_Cx_OTHER register fields */
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#define CM_GCR_Cx_OTHER_CORENUM_SHF 16
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#define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16)
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#define CM3_GCR_Cx_OTHER_CORE_SHF 8
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#define CM3_GCR_Cx_OTHER_CORE_MSK (_ULCAST_(0x3f) << 8)
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#define CM3_GCR_Cx_OTHER_VP_SHF 0
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#define CM3_GCR_Cx_OTHER_VP_MSK (_ULCAST_(0x7) << 0)
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/* GCR_Cx_RESET_BASE register fields */
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#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF 12
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#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12)
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/* GCR_Cx_RESET_EXT_BASE register fields */
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#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF 31
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#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31)
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#define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF 30
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#define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30)
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#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20
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#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20)
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#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF 1
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#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1)
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#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF 0
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#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0)
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/**
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* mips_cm_numcores - return the number of cores present in the system
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*
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* Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
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* zero if no Coherence Manager is present.
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*/
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static inline unsigned mips_cm_numcores(void)
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{
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if (!mips_cm_present())
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return 0;
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return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK)
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>> CM_GCR_CONFIG_PCORES_SHF) + 1;
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}
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|
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/**
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* mips_cm_numiocu - return the number of IOCUs present in the system
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|
*
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* Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
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* if no Coherence Manager is present.
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|
*/
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static inline unsigned mips_cm_numiocu(void)
|
|
{
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if (!mips_cm_present())
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return 0;
|
|
|
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return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK)
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|
>> CM_GCR_CONFIG_NUMIOCU_SHF;
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|
}
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|
|
|
/**
|
|
* mips_cm_l2sync - perform an L2-only sync operation
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|
*
|
|
* If an L2-only sync region is present in the system then this function
|
|
* performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
|
|
*/
|
|
static inline int mips_cm_l2sync(void)
|
|
{
|
|
if (!mips_cm_has_l2sync())
|
|
return -ENODEV;
|
|
|
|
writel(0, mips_cm_l2sync_base);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mips_cm_revision() - return CM revision
|
|
*
|
|
* Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
|
|
* return value should be checked against the CM_REV_* macros.
|
|
*/
|
|
static inline int mips_cm_revision(void)
|
|
{
|
|
if (!mips_cm_present())
|
|
return 0;
|
|
|
|
return read_gcr_rev();
|
|
}
|
|
|
|
/**
|
|
* mips_cm_max_vp_width() - return the width in bits of VP indices
|
|
*
|
|
* Return: the width, in bits, of VP indices in fields that combine core & VP
|
|
* indices.
|
|
*/
|
|
static inline unsigned int mips_cm_max_vp_width(void)
|
|
{
|
|
extern int smp_num_siblings;
|
|
|
|
if (mips_cm_revision() >= CM_REV_CM3)
|
|
return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK;
|
|
|
|
return smp_num_siblings;
|
|
}
|
|
|
|
/**
|
|
* mips_cm_vp_id() - calculate the hardware VP ID for a CPU
|
|
* @cpu: the CPU whose VP ID to calculate
|
|
*
|
|
* Hardware such as the GIC uses identifiers for VPs which may not match the
|
|
* CPU numbers used by Linux. This function calculates the hardware VP
|
|
* identifier corresponding to a given CPU.
|
|
*
|
|
* Return: the VP ID for the CPU.
|
|
*/
|
|
static inline unsigned int mips_cm_vp_id(unsigned int cpu)
|
|
{
|
|
unsigned int core = cpu_data[cpu].core;
|
|
unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
|
|
|
|
return (core * mips_cm_max_vp_width()) + vp;
|
|
}
|
|
|
|
#ifdef CONFIG_MIPS_CM
|
|
|
|
/**
|
|
* mips_cm_lock_other - lock access to another core
|
|
* @core: the other core to be accessed
|
|
* @vp: the VP within the other core to be accessed
|
|
*
|
|
* Call before operating upon a core via the 'other' register region in
|
|
* order to prevent the region being moved during access. Must be followed
|
|
* by a call to mips_cm_unlock_other.
|
|
*/
|
|
extern void mips_cm_lock_other(unsigned int core, unsigned int vp);
|
|
|
|
/**
|
|
* mips_cm_unlock_other - unlock access to another core
|
|
*
|
|
* Call after operating upon another core via the 'other' register region.
|
|
* Must be called after mips_cm_lock_other.
|
|
*/
|
|
extern void mips_cm_unlock_other(void);
|
|
|
|
#else /* !CONFIG_MIPS_CM */
|
|
|
|
static inline void mips_cm_lock_other(unsigned int core) { }
|
|
static inline void mips_cm_unlock_other(void) { }
|
|
|
|
#endif /* !CONFIG_MIPS_CM */
|
|
|
|
#endif /* __MIPS_ASM_MIPS_CM_H__ */
|