mirror of https://gitee.com/openkylin/linux.git
384 lines
12 KiB
C
384 lines
12 KiB
C
/*
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* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2015 Glider bvba
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*
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* Based on clk-rcar-gen3.c
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/bug.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_EXTALR,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL3,
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CLK_PLL4,
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CLK_PLL1_DIV2,
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CLK_PLL1_DIV4,
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CLK_S0,
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CLK_S1,
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_SSPSRC,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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enum r8a7795_clk_types {
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CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_GEN3_PLL0,
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CLK_TYPE_GEN3_PLL1,
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CLK_TYPE_GEN3_PLL2,
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CLK_TYPE_GEN3_PLL3,
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CLK_TYPE_GEN3_PLL4,
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};
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static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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/* Core Clock Outputs */
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DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
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DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
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DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
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DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
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DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
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DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
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DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
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DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
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DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
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DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
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DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
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DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
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};
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static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
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DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
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DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
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DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
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DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
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DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
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DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
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DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
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DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
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DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
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DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
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DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1),
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DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
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DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
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DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
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DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
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DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
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DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
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DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
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DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
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DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
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DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
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DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
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DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1),
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DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1),
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DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
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DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1),
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DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1),
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DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1),
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DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1),
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DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1),
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DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1),
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DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
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DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
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DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
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DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
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DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
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DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
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DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
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DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
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DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
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DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
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DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2),
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DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
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DEF_MOD("gpio7", 905, R8A7795_CLK_CP),
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DEF_MOD("gpio6", 906, R8A7795_CLK_CP),
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DEF_MOD("gpio5", 907, R8A7795_CLK_CP),
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DEF_MOD("gpio4", 908, R8A7795_CLK_CP),
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DEF_MOD("gpio3", 909, R8A7795_CLK_CP),
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DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
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DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
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DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
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DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
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DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
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DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
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DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2),
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DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
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DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
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DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
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DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
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DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
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DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
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DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
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DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
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DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
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DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
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DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
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DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
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DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
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DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
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DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
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DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
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DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
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DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
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DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
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};
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static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
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MOD_CLK_ID(408), /* INTC-AP (GIC) */
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};
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#define CPG_PLL0CR 0x00d8
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#define CPG_PLL2CR 0x002c
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#define CPG_PLL4CR 0x01f4
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/*
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* CPG Clock Data
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*/
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/*
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* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
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* 14 13 19 17 (MHz)
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*-------------------------------------------------------------------
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* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
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* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
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* 0 0 1 0 Prohibited setting
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* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
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* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
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* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
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* 0 1 1 0 Prohibited setting
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* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
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* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
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* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
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* 1 0 1 0 Prohibited setting
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* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
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* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
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* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
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* 1 1 1 0 Prohibited setting
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* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
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(((md) & BIT(13)) >> 11) | \
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(((md) & BIT(19)) >> 18) | \
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(((md) & BIT(17)) >> 17))
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struct cpg_pll_config {
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unsigned int extal_div;
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unsigned int pll1_mult;
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unsigned int pll3_mult;
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};
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static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
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/* EXTAL div PLL1 mult PLL3 mult */
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{ 1, 192, 192, },
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{ 1, 192, 128, },
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{ 0, /* Prohibited setting */ },
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{ 1, 192, 192, },
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{ 1, 160, 160, },
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{ 1, 160, 106, },
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{ 0, /* Prohibited setting */ },
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{ 1, 160, 160, },
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{ 1, 128, 128, },
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{ 1, 128, 84, },
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{ 0, /* Prohibited setting */ },
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{ 1, 128, 128, },
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{ 2, 192, 192, },
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{ 2, 192, 128, },
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{ 0, /* Prohibited setting */ },
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{ 2, 192, 192, },
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};
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static const struct cpg_pll_config *cpg_pll_config __initdata;
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static
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struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core,
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const struct cpg_mssr_info *info,
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struct clk **clks,
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void __iomem *base)
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{
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const struct clk *parent;
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unsigned int mult = 1;
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unsigned int div = 1;
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u32 value;
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parent = clks[core->parent];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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switch (core->type) {
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case CLK_TYPE_GEN3_MAIN:
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div = cpg_pll_config->extal_div;
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break;
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case CLK_TYPE_GEN3_PLL0:
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/*
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* PLL0 is a configurable multiplier clock. Register it as a
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* fixed factor clock for now as there's no generic multiplier
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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value = readl(base + CPG_PLL0CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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break;
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case CLK_TYPE_GEN3_PLL1:
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mult = cpg_pll_config->pll1_mult;
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break;
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case CLK_TYPE_GEN3_PLL2:
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/*
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* PLL2 is a configurable multiplier clock. Register it as a
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* fixed factor clock for now as there's no generic multiplier
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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value = readl(base + CPG_PLL2CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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break;
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case CLK_TYPE_GEN3_PLL3:
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mult = cpg_pll_config->pll3_mult;
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break;
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case CLK_TYPE_GEN3_PLL4:
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/*
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* PLL4 is a configurable multiplier clock. Register it as a
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* fixed factor clock for now as there's no generic multiplier
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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value = readl(base + CPG_PLL4CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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return clk_register_fixed_factor(NULL, core->name,
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__clk_get_name(parent), 0, mult, div);
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}
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/*
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* Reset register definitions.
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*/
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#define MODEMR 0xe6160060
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static u32 rcar_gen3_read_mode_pins(void)
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{
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void __iomem *modemr = ioremap_nocache(MODEMR, 4);
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u32 mode;
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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return mode;
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}
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static int __init r8a7795_cpg_mssr_init(struct device *dev)
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{
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u32 cpg_mode = rcar_gen3_read_mode_pins();
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cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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if (!cpg_pll_config->extal_div) {
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dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
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return -EINVAL;
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}
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return 0;
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}
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const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
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/* Core Clocks */
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.core_clks = r8a7795_core_clks,
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.num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r8a7795_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
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.num_hw_mod_clks = 12 * 32,
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/* Critical Module Clocks */
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.crit_mod_clks = r8a7795_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
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/* Callbacks */
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.init = r8a7795_cpg_mssr_init,
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.cpg_clk_register = r8a7795_cpg_clk_register,
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};
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