mirror of https://gitee.com/openkylin/linux.git
531 lines
14 KiB
C
531 lines
14 KiB
C
/*
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* omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
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*
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* Copyright (C) 2009-2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The data in this file should be completely autogeneratable from
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* the TI hardware database or other technical documentation.
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*
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* XXX these should be marked initdata for multi-OMAP kernels
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*/
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#include <plat/omap_hwmod.h>
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#include <mach/irqs.h>
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#include <plat/cpu.h>
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#include <plat/dma.h>
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#include <plat/serial.h>
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#include "omap_hwmod_common_data.h"
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#include "prm-regbits-34xx.h"
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#include "cm-regbits-34xx.h"
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/*
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* OMAP3xxx hardware module integration data
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*
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* ALl of the data in this section should be autogeneratable from the
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* TI hardware database or other technical documentation. Data that
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* is driver-specific or driver-kernel integration-specific belongs
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* elsewhere.
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*/
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static struct omap_hwmod omap3xxx_mpu_hwmod;
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static struct omap_hwmod omap3xxx_iva_hwmod;
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static struct omap_hwmod omap3xxx_l3_main_hwmod;
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static struct omap_hwmod omap3xxx_l4_core_hwmod;
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static struct omap_hwmod omap3xxx_l4_per_hwmod;
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static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
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/* L3 -> L4_CORE interface */
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static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
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.master = &omap3xxx_l3_main_hwmod,
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.slave = &omap3xxx_l4_core_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L3 -> L4_PER interface */
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static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
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.master = &omap3xxx_l3_main_hwmod,
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.slave = &omap3xxx_l4_per_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* MPU -> L3 interface */
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static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
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.master = &omap3xxx_mpu_hwmod,
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.slave = &omap3xxx_l3_main_hwmod,
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.user = OCP_USER_MPU,
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};
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/* Slave interfaces on the L3 interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
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&omap3xxx_mpu__l3_main,
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};
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/* Master interfaces on the L3 interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
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&omap3xxx_l3_main__l4_core,
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&omap3xxx_l3_main__l4_per,
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};
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/* L3 */
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static struct omap_hwmod omap3xxx_l3_main_hwmod = {
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.name = "l3_main",
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.class = &l3_hwmod_class,
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.masters = omap3xxx_l3_main_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
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.slaves = omap3xxx_l3_main_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.flags = HWMOD_NO_IDLEST,
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};
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static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
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static struct omap_hwmod omap3xxx_uart1_hwmod;
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static struct omap_hwmod omap3xxx_uart2_hwmod;
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static struct omap_hwmod omap3xxx_uart3_hwmod;
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static struct omap_hwmod omap3xxx_uart4_hwmod;
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/* L4_CORE -> L4_WKUP interface */
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static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_l4_wkup_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> UART1 interface */
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static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
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{
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.pa_start = OMAP3_UART1_BASE,
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.pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_uart1_hwmod,
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.clk = "uart1_ick",
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.addr = omap3xxx_uart1_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> UART2 interface */
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static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
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{
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.pa_start = OMAP3_UART2_BASE,
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.pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_uart2_hwmod,
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.clk = "uart2_ick",
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.addr = omap3xxx_uart2_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 PER -> UART3 interface */
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static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
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{
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.pa_start = OMAP3_UART3_BASE,
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.pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
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.master = &omap3xxx_l4_per_hwmod,
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.slave = &omap3xxx_uart3_hwmod,
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.clk = "uart3_ick",
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.addr = omap3xxx_uart3_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 PER -> UART4 interface */
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static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
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{
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.pa_start = OMAP3_UART4_BASE,
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.pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
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.master = &omap3xxx_l4_per_hwmod,
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.slave = &omap3xxx_uart4_hwmod,
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.clk = "uart4_ick",
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.addr = omap3xxx_uart4_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* Slave interfaces on the L4_CORE interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
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&omap3xxx_l3_main__l4_core,
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};
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/* Master interfaces on the L4_CORE interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
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&omap3xxx_l4_core__l4_wkup,
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&omap3_l4_core__uart1,
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&omap3_l4_core__uart2,
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};
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/* L4 CORE */
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static struct omap_hwmod omap3xxx_l4_core_hwmod = {
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.name = "l4_core",
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.class = &l4_hwmod_class,
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.masters = omap3xxx_l4_core_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
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.slaves = omap3xxx_l4_core_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.flags = HWMOD_NO_IDLEST,
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};
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/* Slave interfaces on the L4_PER interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
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&omap3xxx_l3_main__l4_per,
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};
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/* Master interfaces on the L4_PER interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
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&omap3_l4_per__uart3,
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&omap3_l4_per__uart4,
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};
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/* L4 PER */
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static struct omap_hwmod omap3xxx_l4_per_hwmod = {
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.name = "l4_per",
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.class = &l4_hwmod_class,
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.masters = omap3xxx_l4_per_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
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.slaves = omap3xxx_l4_per_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.flags = HWMOD_NO_IDLEST,
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};
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/* Slave interfaces on the L4_WKUP interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
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&omap3xxx_l4_core__l4_wkup,
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};
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/* Master interfaces on the L4_WKUP interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
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};
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/* L4 WKUP */
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static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
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.name = "l4_wkup",
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.class = &l4_hwmod_class,
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.masters = omap3xxx_l4_wkup_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
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.slaves = omap3xxx_l4_wkup_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.flags = HWMOD_NO_IDLEST,
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};
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/* Master interfaces on the MPU device */
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static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
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&omap3xxx_mpu__l3_main,
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};
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/* MPU */
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static struct omap_hwmod omap3xxx_mpu_hwmod = {
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.name = "mpu",
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.class = &mpu_hwmod_class,
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.main_clk = "arm_fck",
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.masters = omap3xxx_mpu_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/*
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* IVA2_2 interface data
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*/
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/* IVA2 <- L3 interface */
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static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
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.master = &omap3xxx_l3_main_hwmod,
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.slave = &omap3xxx_iva_hwmod,
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.clk = "iva2_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
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&omap3xxx_l3__iva,
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};
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/*
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* IVA2 (IVA2)
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*/
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static struct omap_hwmod omap3xxx_iva_hwmod = {
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.name = "iva",
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.class = &iva_hwmod_class,
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.masters = omap3xxx_iva_masters,
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.masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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};
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/* l4_wkup -> wd_timer2 */
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static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
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{
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.pa_start = 0x48314000,
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.pa_end = 0x4831407f,
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.flags = ADDR_TYPE_RT
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},
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};
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static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
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.master = &omap3xxx_l4_wkup_hwmod,
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.slave = &omap3xxx_wd_timer2_hwmod,
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.clk = "wdt2_ick",
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.addr = omap3xxx_wd_timer2_addrs,
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.addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/*
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* 'wd_timer' class
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* 32-bit watchdog upward counter that generates a pulse on the reset pin on
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* overflow condition
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*/
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static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
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.name = "wd_timer",
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.sysc = &omap3xxx_wd_timer_sysc,
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};
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/* wd_timer2 */
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static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
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&omap3xxx_l4_wkup__wd_timer2,
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};
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static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
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.name = "wd_timer2",
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.class = &omap3xxx_wd_timer_hwmod_class,
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.main_clk = "wdt2_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_WDT2_SHIFT,
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
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},
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},
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.slaves = omap3xxx_wd_timer2_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/* UART common */
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static struct omap_hwmod_class_sysconfig uart_sysc = {
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.rev_offs = 0x50,
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.sysc_offs = 0x54,
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.syss_offs = 0x58,
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.sysc_flags = (SYSC_HAS_SIDLEMODE |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class uart_class = {
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.name = "uart",
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.sysc = &uart_sysc,
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};
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/* UART1 */
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static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
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{ .irq = INT_24XX_UART1_IRQ, },
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};
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static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
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{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
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{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
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&omap3_l4_core__uart1,
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};
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static struct omap_hwmod omap3xxx_uart1_hwmod = {
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.name = "uart1",
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.mpu_irqs = uart1_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
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.sdma_reqs = uart1_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
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.main_clk = "uart1_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_UART1_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
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},
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},
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.slaves = omap3xxx_uart1_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
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.class = &uart_class,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/* UART2 */
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static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
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{ .irq = INT_24XX_UART2_IRQ, },
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};
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static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
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{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
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{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
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&omap3_l4_core__uart2,
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};
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static struct omap_hwmod omap3xxx_uart2_hwmod = {
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.name = "uart2",
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.mpu_irqs = uart2_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
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.sdma_reqs = uart2_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
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.main_clk = "uart2_fck",
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.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_UART2_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_uart2_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
|
|
.class = &uart_class,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* UART3 */
|
|
|
|
static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
|
|
{ .irq = INT_24XX_UART3_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
|
|
&omap3_l4_per__uart3,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_uart3_hwmod = {
|
|
.name = "uart3",
|
|
.mpu_irqs = uart3_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
|
|
.sdma_reqs = uart3_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
|
|
.main_clk = "uart3_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = OMAP3430_PER_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3430_EN_UART3_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_uart3_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
|
|
.class = &uart_class,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* UART4 */
|
|
|
|
static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
|
|
{ .irq = INT_36XX_UART4_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
|
|
{ .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
|
|
{ .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
|
|
&omap3_l4_per__uart4,
|
|
};
|
|
|
|
static struct omap_hwmod omap3xxx_uart4_hwmod = {
|
|
.name = "uart4",
|
|
.mpu_irqs = uart4_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
|
|
.sdma_reqs = uart4_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
|
|
.main_clk = "uart4_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = OMAP3430_PER_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP3630_EN_UART4_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap3xxx_uart4_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
|
|
.class = &uart_class,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
|
|
};
|
|
|
|
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
|
&omap3xxx_l3_main_hwmod,
|
|
&omap3xxx_l4_core_hwmod,
|
|
&omap3xxx_l4_per_hwmod,
|
|
&omap3xxx_l4_wkup_hwmod,
|
|
&omap3xxx_mpu_hwmod,
|
|
&omap3xxx_iva_hwmod,
|
|
&omap3xxx_wd_timer2_hwmod,
|
|
&omap3xxx_uart1_hwmod,
|
|
&omap3xxx_uart2_hwmod,
|
|
&omap3xxx_uart3_hwmod,
|
|
&omap3xxx_uart4_hwmod,
|
|
NULL,
|
|
};
|
|
|
|
int __init omap3xxx_hwmod_init(void)
|
|
{
|
|
return omap_hwmod_init(omap3xxx_hwmods);
|
|
}
|