mirror of https://gitee.com/openkylin/linux.git
1089 lines
28 KiB
C
1089 lines
28 KiB
C
#include <linux/bitops.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <asm/perf_event.h>
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#include <asm/insn.h>
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#include "perf_event.h"
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/* The size of a BTS record in bytes: */
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#define BTS_RECORD_SIZE 24
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#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
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#define PEBS_BUFFER_SIZE PAGE_SIZE
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#define PEBS_FIXUP_SIZE PAGE_SIZE
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/*
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* pebs_record_32 for p4 and core not supported
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struct pebs_record_32 {
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u32 flags, ip;
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u32 ax, bc, cx, dx;
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u32 si, di, bp, sp;
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};
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*/
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union intel_x86_pebs_dse {
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u64 val;
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struct {
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unsigned int ld_dse:4;
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unsigned int ld_stlb_miss:1;
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unsigned int ld_locked:1;
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unsigned int ld_reserved:26;
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};
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struct {
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unsigned int st_l1d_hit:1;
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unsigned int st_reserved1:3;
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unsigned int st_stlb_miss:1;
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unsigned int st_locked:1;
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unsigned int st_reserved2:26;
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};
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};
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/*
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* Map PEBS Load Latency Data Source encodings to generic
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* memory data source information
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*/
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#define P(a, b) PERF_MEM_S(a, b)
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#define OP_LH (P(OP, LOAD) | P(LVL, HIT))
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#define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
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static const u64 pebs_data_source[] = {
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P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
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OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
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OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
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OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
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OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
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OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
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OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
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OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
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OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
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OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
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OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
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OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
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OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
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OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
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OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
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OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
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};
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static u64 precise_store_data(u64 status)
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{
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union intel_x86_pebs_dse dse;
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u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
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dse.val = status;
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/*
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* bit 4: TLB access
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* 1 = stored missed 2nd level TLB
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*
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* so it either hit the walker or the OS
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* otherwise hit 2nd level TLB
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*/
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if (dse.st_stlb_miss)
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val |= P(TLB, MISS);
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else
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val |= P(TLB, HIT);
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/*
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* bit 0: hit L1 data cache
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* if not set, then all we know is that
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* it missed L1D
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*/
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if (dse.st_l1d_hit)
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val |= P(LVL, HIT);
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else
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val |= P(LVL, MISS);
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/*
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* bit 5: Locked prefix
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*/
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if (dse.st_locked)
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val |= P(LOCK, LOCKED);
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return val;
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}
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static u64 precise_store_data_hsw(u64 status)
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{
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union perf_mem_data_src dse;
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dse.val = 0;
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dse.mem_op = PERF_MEM_OP_STORE;
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dse.mem_lvl = PERF_MEM_LVL_NA;
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if (status & 1)
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dse.mem_lvl = PERF_MEM_LVL_L1;
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/* Nothing else supported. Sorry. */
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return dse.val;
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}
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static u64 load_latency_data(u64 status)
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{
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union intel_x86_pebs_dse dse;
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u64 val;
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int model = boot_cpu_data.x86_model;
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int fam = boot_cpu_data.x86;
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dse.val = status;
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/*
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* use the mapping table for bit 0-3
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*/
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val = pebs_data_source[dse.ld_dse];
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/*
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* Nehalem models do not support TLB, Lock infos
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*/
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if (fam == 0x6 && (model == 26 || model == 30
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|| model == 31 || model == 46)) {
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val |= P(TLB, NA) | P(LOCK, NA);
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return val;
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}
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/*
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* bit 4: TLB access
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* 0 = did not miss 2nd level TLB
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* 1 = missed 2nd level TLB
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*/
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if (dse.ld_stlb_miss)
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val |= P(TLB, MISS) | P(TLB, L2);
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else
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val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
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/*
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* bit 5: locked prefix
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*/
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if (dse.ld_locked)
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val |= P(LOCK, LOCKED);
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return val;
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}
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struct pebs_record_core {
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u64 flags, ip;
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u64 ax, bx, cx, dx;
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u64 si, di, bp, sp;
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u64 r8, r9, r10, r11;
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u64 r12, r13, r14, r15;
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};
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struct pebs_record_nhm {
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u64 flags, ip;
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u64 ax, bx, cx, dx;
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u64 si, di, bp, sp;
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u64 r8, r9, r10, r11;
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u64 r12, r13, r14, r15;
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u64 status, dla, dse, lat;
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};
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/*
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* Same as pebs_record_nhm, with two additional fields.
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*/
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struct pebs_record_hsw {
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u64 flags, ip;
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u64 ax, bx, cx, dx;
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u64 si, di, bp, sp;
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u64 r8, r9, r10, r11;
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u64 r12, r13, r14, r15;
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u64 status, dla, dse, lat;
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u64 real_ip, tsx_tuning;
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};
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union hsw_tsx_tuning {
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struct {
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u32 cycles_last_block : 32,
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hle_abort : 1,
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rtm_abort : 1,
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instruction_abort : 1,
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non_instruction_abort : 1,
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retry : 1,
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data_conflict : 1,
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capacity_writes : 1,
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capacity_reads : 1;
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};
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u64 value;
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};
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#define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
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void init_debug_store_on_cpu(int cpu)
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{
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struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
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if (!ds)
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return;
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wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
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(u32)((u64)(unsigned long)ds),
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(u32)((u64)(unsigned long)ds >> 32));
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}
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void fini_debug_store_on_cpu(int cpu)
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{
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if (!per_cpu(cpu_hw_events, cpu).ds)
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return;
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wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
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}
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static DEFINE_PER_CPU(void *, insn_buffer);
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static int alloc_pebs_buffer(int cpu)
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{
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struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
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int node = cpu_to_node(cpu);
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int max, thresh = 1; /* always use a single PEBS record */
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void *buffer, *ibuffer;
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if (!x86_pmu.pebs)
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return 0;
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buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
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if (unlikely(!buffer))
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return -ENOMEM;
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/*
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* HSW+ already provides us the eventing ip; no need to allocate this
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* buffer then.
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*/
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if (x86_pmu.intel_cap.pebs_format < 2) {
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ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
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if (!ibuffer) {
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kfree(buffer);
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return -ENOMEM;
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}
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per_cpu(insn_buffer, cpu) = ibuffer;
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}
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max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
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ds->pebs_buffer_base = (u64)(unsigned long)buffer;
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ds->pebs_index = ds->pebs_buffer_base;
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ds->pebs_absolute_maximum = ds->pebs_buffer_base +
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max * x86_pmu.pebs_record_size;
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ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
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thresh * x86_pmu.pebs_record_size;
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return 0;
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}
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static void release_pebs_buffer(int cpu)
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{
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struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
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if (!ds || !x86_pmu.pebs)
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return;
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kfree(per_cpu(insn_buffer, cpu));
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per_cpu(insn_buffer, cpu) = NULL;
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kfree((void *)(unsigned long)ds->pebs_buffer_base);
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ds->pebs_buffer_base = 0;
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}
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static int alloc_bts_buffer(int cpu)
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{
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struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
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int node = cpu_to_node(cpu);
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int max, thresh;
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void *buffer;
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if (!x86_pmu.bts)
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return 0;
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buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL, node);
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if (unlikely(!buffer))
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return -ENOMEM;
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max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
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thresh = max / 16;
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ds->bts_buffer_base = (u64)(unsigned long)buffer;
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ds->bts_index = ds->bts_buffer_base;
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ds->bts_absolute_maximum = ds->bts_buffer_base +
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max * BTS_RECORD_SIZE;
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ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
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thresh * BTS_RECORD_SIZE;
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return 0;
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}
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static void release_bts_buffer(int cpu)
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{
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struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
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if (!ds || !x86_pmu.bts)
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return;
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kfree((void *)(unsigned long)ds->bts_buffer_base);
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ds->bts_buffer_base = 0;
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}
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static int alloc_ds_buffer(int cpu)
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{
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int node = cpu_to_node(cpu);
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struct debug_store *ds;
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ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
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if (unlikely(!ds))
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return -ENOMEM;
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per_cpu(cpu_hw_events, cpu).ds = ds;
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return 0;
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}
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static void release_ds_buffer(int cpu)
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{
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struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
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if (!ds)
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return;
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per_cpu(cpu_hw_events, cpu).ds = NULL;
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kfree(ds);
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}
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void release_ds_buffers(void)
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{
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int cpu;
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if (!x86_pmu.bts && !x86_pmu.pebs)
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return;
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get_online_cpus();
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for_each_online_cpu(cpu)
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fini_debug_store_on_cpu(cpu);
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for_each_possible_cpu(cpu) {
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release_pebs_buffer(cpu);
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release_bts_buffer(cpu);
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release_ds_buffer(cpu);
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}
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put_online_cpus();
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}
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void reserve_ds_buffers(void)
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{
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int bts_err = 0, pebs_err = 0;
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int cpu;
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x86_pmu.bts_active = 0;
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x86_pmu.pebs_active = 0;
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if (!x86_pmu.bts && !x86_pmu.pebs)
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return;
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if (!x86_pmu.bts)
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bts_err = 1;
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if (!x86_pmu.pebs)
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pebs_err = 1;
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get_online_cpus();
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for_each_possible_cpu(cpu) {
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if (alloc_ds_buffer(cpu)) {
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bts_err = 1;
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pebs_err = 1;
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}
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if (!bts_err && alloc_bts_buffer(cpu))
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bts_err = 1;
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if (!pebs_err && alloc_pebs_buffer(cpu))
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pebs_err = 1;
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if (bts_err && pebs_err)
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break;
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}
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if (bts_err) {
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for_each_possible_cpu(cpu)
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release_bts_buffer(cpu);
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}
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if (pebs_err) {
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for_each_possible_cpu(cpu)
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release_pebs_buffer(cpu);
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}
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if (bts_err && pebs_err) {
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for_each_possible_cpu(cpu)
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release_ds_buffer(cpu);
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} else {
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if (x86_pmu.bts && !bts_err)
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x86_pmu.bts_active = 1;
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if (x86_pmu.pebs && !pebs_err)
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x86_pmu.pebs_active = 1;
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for_each_online_cpu(cpu)
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init_debug_store_on_cpu(cpu);
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}
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put_online_cpus();
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}
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/*
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* BTS
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*/
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struct event_constraint bts_constraint =
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EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
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void intel_pmu_enable_bts(u64 config)
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{
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unsigned long debugctlmsr;
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debugctlmsr = get_debugctlmsr();
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debugctlmsr |= DEBUGCTLMSR_TR;
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debugctlmsr |= DEBUGCTLMSR_BTS;
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debugctlmsr |= DEBUGCTLMSR_BTINT;
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if (!(config & ARCH_PERFMON_EVENTSEL_OS))
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debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
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if (!(config & ARCH_PERFMON_EVENTSEL_USR))
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debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
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update_debugctlmsr(debugctlmsr);
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}
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void intel_pmu_disable_bts(void)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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unsigned long debugctlmsr;
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if (!cpuc->ds)
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return;
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debugctlmsr = get_debugctlmsr();
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debugctlmsr &=
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~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
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DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
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update_debugctlmsr(debugctlmsr);
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}
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int intel_pmu_drain_bts_buffer(void)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct debug_store *ds = cpuc->ds;
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struct bts_record {
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u64 from;
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u64 to;
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u64 flags;
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};
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struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
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struct bts_record *at, *top;
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struct perf_output_handle handle;
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struct perf_event_header header;
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struct perf_sample_data data;
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struct pt_regs regs;
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if (!event)
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return 0;
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if (!x86_pmu.bts_active)
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return 0;
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at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
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top = (struct bts_record *)(unsigned long)ds->bts_index;
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if (top <= at)
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return 0;
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memset(®s, 0, sizeof(regs));
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ds->bts_index = ds->bts_buffer_base;
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perf_sample_data_init(&data, 0, event->hw.last_period);
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/*
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* Prepare a generic sample, i.e. fill in the invariant fields.
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* We will overwrite the from and to address before we output
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* the sample.
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*/
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perf_prepare_sample(&header, &data, event, ®s);
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if (perf_output_begin(&handle, event, header.size * (top - at)))
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return 1;
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for (; at < top; at++) {
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data.ip = at->from;
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data.addr = at->to;
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|
|
perf_output_sample(&handle, &header, &data, event);
|
|
}
|
|
|
|
perf_output_end(&handle);
|
|
|
|
/* There's new data available. */
|
|
event->hw.interrupts++;
|
|
event->pending_kill = POLL_IN;
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* PEBS
|
|
*/
|
|
struct event_constraint intel_core2_pebs_event_constraints[] = {
|
|
INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
|
|
INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
|
|
INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
|
|
INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
|
|
INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
|
|
EVENT_CONSTRAINT_END
|
|
};
|
|
|
|
struct event_constraint intel_atom_pebs_event_constraints[] = {
|
|
INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
|
|
INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
|
|
INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
|
|
EVENT_CONSTRAINT_END
|
|
};
|
|
|
|
struct event_constraint intel_slm_pebs_event_constraints[] = {
|
|
INTEL_UEVENT_CONSTRAINT(0x0103, 0x1), /* REHABQ.LD_BLOCK_ST_FORWARD_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0x0803, 0x1), /* REHABQ.LD_SPLITS_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0x0204, 0x1), /* MEM_UOPS_RETIRED.L2_HIT_LOADS_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0x0404, 0x1), /* MEM_UOPS_RETIRED.L2_MISS_LOADS_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0x0804, 0x1), /* MEM_UOPS_RETIRED.DTLB_MISS_LOADS_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0x2004, 0x1), /* MEM_UOPS_RETIRED.HITM_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0x00c4, 0x1), /* BR_INST_RETIRED.ALL_BRANCHES_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0x7ec4, 0x1), /* BR_INST_RETIRED.JCC_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xbfc4, 0x1), /* BR_INST_RETIRED.FAR_BRANCH_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xebc4, 0x1), /* BR_INST_RETIRED.NON_RETURN_IND_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xf7c4, 0x1), /* BR_INST_RETIRED.RETURN_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xf9c4, 0x1), /* BR_INST_RETIRED.CALL_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xfbc4, 0x1), /* BR_INST_RETIRED.IND_CALL_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xfdc4, 0x1), /* BR_INST_RETIRED.REL_CALL_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xfec4, 0x1), /* BR_INST_RETIRED.TAKEN_JCC_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_MISP_RETIRED.ALL_BRANCHES_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0x7ec5, 0x1), /* BR_INST_MISP_RETIRED.JCC_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xebc5, 0x1), /* BR_INST_MISP_RETIRED.NON_RETURN_IND_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xf7c5, 0x1), /* BR_INST_MISP_RETIRED.RETURN_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xfbc5, 0x1), /* BR_INST_MISP_RETIRED.IND_CALL_PS */
|
|
INTEL_UEVENT_CONSTRAINT(0xfec5, 0x1), /* BR_INST_MISP_RETIRED.TAKEN_JCC_PS */
|
|
EVENT_CONSTRAINT_END
|
|
};
|
|
|
|
struct event_constraint intel_nehalem_pebs_event_constraints[] = {
|
|
INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
|
|
INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
|
|
INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
|
|
INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
|
|
INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
|
|
INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
|
|
INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
|
|
INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
|
|
EVENT_CONSTRAINT_END
|
|
};
|
|
|
|
struct event_constraint intel_westmere_pebs_event_constraints[] = {
|
|
INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
|
|
INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
|
|
INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
|
|
INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
|
|
INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
|
|
EVENT_CONSTRAINT_END
|
|
};
|
|
|
|
struct event_constraint intel_snb_pebs_event_constraints[] = {
|
|
INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
|
|
INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
|
|
INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
|
|
INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
|
|
INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
|
|
INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
|
|
INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
|
|
INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
|
|
EVENT_CONSTRAINT_END
|
|
};
|
|
|
|
struct event_constraint intel_ivb_pebs_event_constraints[] = {
|
|
INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
|
|
INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
|
|
INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
|
|
INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
|
|
INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
|
|
INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
|
|
INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
|
|
INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
|
|
EVENT_CONSTRAINT_END
|
|
};
|
|
|
|
struct event_constraint intel_hsw_pebs_event_constraints[] = {
|
|
INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
|
|
INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
|
|
INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
|
|
INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
|
|
INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
|
|
INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
|
|
INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
|
|
INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.* */
|
|
/* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
|
|
INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf),
|
|
/* MEM_UOPS_RETIRED.STLB_MISS_STORES */
|
|
INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf),
|
|
INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
|
|
INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
|
|
/* MEM_UOPS_RETIRED.SPLIT_STORES */
|
|
INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf),
|
|
INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
|
|
INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
|
|
INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
|
|
INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
|
|
INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
|
|
/* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
|
|
INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf),
|
|
/* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
|
|
INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf),
|
|
/* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
|
|
INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf),
|
|
/* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
|
|
INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf),
|
|
INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
|
|
INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
|
|
|
|
EVENT_CONSTRAINT_END
|
|
};
|
|
|
|
struct event_constraint *intel_pebs_constraints(struct perf_event *event)
|
|
{
|
|
struct event_constraint *c;
|
|
|
|
if (!event->attr.precise_ip)
|
|
return NULL;
|
|
|
|
if (x86_pmu.pebs_constraints) {
|
|
for_each_event_constraint(c, x86_pmu.pebs_constraints) {
|
|
if ((event->hw.config & c->cmask) == c->code) {
|
|
event->hw.flags |= c->flags;
|
|
return c;
|
|
}
|
|
}
|
|
}
|
|
|
|
return &emptyconstraint;
|
|
}
|
|
|
|
void intel_pmu_pebs_enable(struct perf_event *event)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
|
|
|
|
cpuc->pebs_enabled |= 1ULL << hwc->idx;
|
|
|
|
if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
|
|
cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
|
|
else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
|
|
cpuc->pebs_enabled |= 1ULL << 63;
|
|
}
|
|
|
|
void intel_pmu_pebs_disable(struct perf_event *event)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
|
|
|
|
if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
|
|
cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
|
|
else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
|
|
cpuc->pebs_enabled &= ~(1ULL << 63);
|
|
|
|
if (cpuc->enabled)
|
|
wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
|
|
|
|
hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
|
|
}
|
|
|
|
void intel_pmu_pebs_enable_all(void)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
|
|
if (cpuc->pebs_enabled)
|
|
wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
|
|
}
|
|
|
|
void intel_pmu_pebs_disable_all(void)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
|
|
if (cpuc->pebs_enabled)
|
|
wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
|
|
}
|
|
|
|
static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
unsigned long from = cpuc->lbr_entries[0].from;
|
|
unsigned long old_to, to = cpuc->lbr_entries[0].to;
|
|
unsigned long ip = regs->ip;
|
|
int is_64bit = 0;
|
|
void *kaddr;
|
|
|
|
/*
|
|
* We don't need to fixup if the PEBS assist is fault like
|
|
*/
|
|
if (!x86_pmu.intel_cap.pebs_trap)
|
|
return 1;
|
|
|
|
/*
|
|
* No LBR entry, no basic block, no rewinding
|
|
*/
|
|
if (!cpuc->lbr_stack.nr || !from || !to)
|
|
return 0;
|
|
|
|
/*
|
|
* Basic blocks should never cross user/kernel boundaries
|
|
*/
|
|
if (kernel_ip(ip) != kernel_ip(to))
|
|
return 0;
|
|
|
|
/*
|
|
* unsigned math, either ip is before the start (impossible) or
|
|
* the basic block is larger than 1 page (sanity)
|
|
*/
|
|
if ((ip - to) > PEBS_FIXUP_SIZE)
|
|
return 0;
|
|
|
|
/*
|
|
* We sampled a branch insn, rewind using the LBR stack
|
|
*/
|
|
if (ip == to) {
|
|
set_linear_ip(regs, from);
|
|
return 1;
|
|
}
|
|
|
|
if (!kernel_ip(ip)) {
|
|
int size, bytes;
|
|
u8 *buf = this_cpu_read(insn_buffer);
|
|
|
|
size = ip - to; /* Must fit our buffer, see above */
|
|
bytes = copy_from_user_nmi(buf, (void __user *)to, size);
|
|
if (bytes != 0)
|
|
return 0;
|
|
|
|
kaddr = buf;
|
|
} else {
|
|
kaddr = (void *)to;
|
|
}
|
|
|
|
do {
|
|
struct insn insn;
|
|
|
|
old_to = to;
|
|
|
|
#ifdef CONFIG_X86_64
|
|
is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
|
|
#endif
|
|
insn_init(&insn, kaddr, is_64bit);
|
|
insn_get_length(&insn);
|
|
|
|
to += insn.length;
|
|
kaddr += insn.length;
|
|
} while (to < ip);
|
|
|
|
if (to == ip) {
|
|
set_linear_ip(regs, old_to);
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* Even though we decoded the basic block, the instruction stream
|
|
* never matched the given IP, either the TO or the IP got corrupted.
|
|
*/
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
|
|
{
|
|
if (pebs->tsx_tuning) {
|
|
union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
|
|
return tsx.cycles_last_block;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
|
|
{
|
|
u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
|
|
|
|
/* For RTM XABORTs also log the abort code from AX */
|
|
if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
|
|
txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
|
|
return txn;
|
|
}
|
|
|
|
static void __intel_pmu_pebs_event(struct perf_event *event,
|
|
struct pt_regs *iregs, void *__pebs)
|
|
{
|
|
/*
|
|
* We cast to the biggest pebs_record but are careful not to
|
|
* unconditionally access the 'extra' entries.
|
|
*/
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
struct pebs_record_hsw *pebs = __pebs;
|
|
struct perf_sample_data data;
|
|
struct pt_regs regs;
|
|
u64 sample_type;
|
|
int fll, fst;
|
|
|
|
if (!intel_pmu_save_and_restart(event))
|
|
return;
|
|
|
|
fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
|
|
fst = event->hw.flags & (PERF_X86_EVENT_PEBS_ST |
|
|
PERF_X86_EVENT_PEBS_ST_HSW);
|
|
|
|
perf_sample_data_init(&data, 0, event->hw.last_period);
|
|
|
|
data.period = event->hw.last_period;
|
|
sample_type = event->attr.sample_type;
|
|
|
|
/*
|
|
* if PEBS-LL or PreciseStore
|
|
*/
|
|
if (fll || fst) {
|
|
/*
|
|
* Use latency for weight (only avail with PEBS-LL)
|
|
*/
|
|
if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
|
|
data.weight = pebs->lat;
|
|
|
|
/*
|
|
* data.data_src encodes the data source
|
|
*/
|
|
if (sample_type & PERF_SAMPLE_DATA_SRC) {
|
|
if (fll)
|
|
data.data_src.val = load_latency_data(pebs->dse);
|
|
else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
|
|
data.data_src.val =
|
|
precise_store_data_hsw(pebs->dse);
|
|
else
|
|
data.data_src.val = precise_store_data(pebs->dse);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* We use the interrupt regs as a base because the PEBS record
|
|
* does not contain a full regs set, specifically it seems to
|
|
* lack segment descriptors, which get used by things like
|
|
* user_mode().
|
|
*
|
|
* In the simple case fix up only the IP and BP,SP regs, for
|
|
* PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
|
|
* A possible PERF_SAMPLE_REGS will have to transfer all regs.
|
|
*/
|
|
regs = *iregs;
|
|
regs.flags = pebs->flags;
|
|
set_linear_ip(®s, pebs->ip);
|
|
regs.bp = pebs->bp;
|
|
regs.sp = pebs->sp;
|
|
|
|
if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
|
|
regs.ip = pebs->real_ip;
|
|
regs.flags |= PERF_EFLAGS_EXACT;
|
|
} else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(®s))
|
|
regs.flags |= PERF_EFLAGS_EXACT;
|
|
else
|
|
regs.flags &= ~PERF_EFLAGS_EXACT;
|
|
|
|
if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
|
|
x86_pmu.intel_cap.pebs_format >= 1)
|
|
data.addr = pebs->dla;
|
|
|
|
if (x86_pmu.intel_cap.pebs_format >= 2) {
|
|
/* Only set the TSX weight when no memory weight. */
|
|
if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll)
|
|
data.weight = intel_hsw_weight(pebs);
|
|
|
|
if (event->attr.sample_type & PERF_SAMPLE_TRANSACTION)
|
|
data.txn = intel_hsw_transaction(pebs);
|
|
}
|
|
|
|
if (has_branch_stack(event))
|
|
data.br_stack = &cpuc->lbr_stack;
|
|
|
|
if (perf_event_overflow(event, &data, ®s))
|
|
x86_pmu_stop(event, 0);
|
|
}
|
|
|
|
static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
struct debug_store *ds = cpuc->ds;
|
|
struct perf_event *event = cpuc->events[0]; /* PMC0 only */
|
|
struct pebs_record_core *at, *top;
|
|
int n;
|
|
|
|
if (!x86_pmu.pebs_active)
|
|
return;
|
|
|
|
at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
|
|
top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
|
|
|
|
/*
|
|
* Whatever else happens, drain the thing
|
|
*/
|
|
ds->pebs_index = ds->pebs_buffer_base;
|
|
|
|
if (!test_bit(0, cpuc->active_mask))
|
|
return;
|
|
|
|
WARN_ON_ONCE(!event);
|
|
|
|
if (!event->attr.precise_ip)
|
|
return;
|
|
|
|
n = top - at;
|
|
if (n <= 0)
|
|
return;
|
|
|
|
/*
|
|
* Should not happen, we program the threshold at 1 and do not
|
|
* set a reset value.
|
|
*/
|
|
WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
|
|
at += n - 1;
|
|
|
|
__intel_pmu_pebs_event(event, iregs, at);
|
|
}
|
|
|
|
static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
struct debug_store *ds = cpuc->ds;
|
|
struct perf_event *event = NULL;
|
|
void *at, *top;
|
|
u64 status = 0;
|
|
int bit;
|
|
|
|
if (!x86_pmu.pebs_active)
|
|
return;
|
|
|
|
at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
|
|
top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
|
|
|
|
ds->pebs_index = ds->pebs_buffer_base;
|
|
|
|
if (unlikely(at > top))
|
|
return;
|
|
|
|
/*
|
|
* Should not happen, we program the threshold at 1 and do not
|
|
* set a reset value.
|
|
*/
|
|
WARN_ONCE(top - at > x86_pmu.max_pebs_events * x86_pmu.pebs_record_size,
|
|
"Unexpected number of pebs records %ld\n",
|
|
(long)(top - at) / x86_pmu.pebs_record_size);
|
|
|
|
for (; at < top; at += x86_pmu.pebs_record_size) {
|
|
struct pebs_record_nhm *p = at;
|
|
|
|
for_each_set_bit(bit, (unsigned long *)&p->status,
|
|
x86_pmu.max_pebs_events) {
|
|
event = cpuc->events[bit];
|
|
if (!test_bit(bit, cpuc->active_mask))
|
|
continue;
|
|
|
|
WARN_ON_ONCE(!event);
|
|
|
|
if (!event->attr.precise_ip)
|
|
continue;
|
|
|
|
if (__test_and_set_bit(bit, (unsigned long *)&status))
|
|
continue;
|
|
|
|
break;
|
|
}
|
|
|
|
if (!event || bit >= x86_pmu.max_pebs_events)
|
|
continue;
|
|
|
|
__intel_pmu_pebs_event(event, iregs, at);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* BTS, PEBS probe and setup
|
|
*/
|
|
|
|
void intel_ds_init(void)
|
|
{
|
|
/*
|
|
* No support for 32bit formats
|
|
*/
|
|
if (!boot_cpu_has(X86_FEATURE_DTES64))
|
|
return;
|
|
|
|
x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
|
|
x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
|
|
if (x86_pmu.pebs) {
|
|
char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
|
|
int format = x86_pmu.intel_cap.pebs_format;
|
|
|
|
switch (format) {
|
|
case 0:
|
|
printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
|
|
x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
|
|
x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
|
|
break;
|
|
|
|
case 1:
|
|
printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
|
|
x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
|
|
x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
|
|
break;
|
|
|
|
case 2:
|
|
pr_cont("PEBS fmt2%c, ", pebs_type);
|
|
x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
|
|
x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
|
|
x86_pmu.pebs = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
void perf_restore_debug_store(void)
|
|
{
|
|
struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
|
|
|
|
if (!x86_pmu.bts && !x86_pmu.pebs)
|
|
return;
|
|
|
|
wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
|
|
}
|