mirror of https://gitee.com/openkylin/linux.git
271 lines
7.7 KiB
C
271 lines
7.7 KiB
C
/* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $
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* pbm.h: UltraSparc PCI controller software state.
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*
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* Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
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*/
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#ifndef __SPARC64_PBM_H
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#define __SPARC64_PBM_H
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/spinlock.h>
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#include <linux/msi.h>
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#include <asm/io.h>
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#include <asm/page.h>
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#include <asm/oplib.h>
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#include <asm/prom.h>
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#include <asm/of_device.h>
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#include <asm/iommu.h>
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/* The abstraction used here is that there are PCI controllers,
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* each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
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* underneath. Each PCI bus module uses an IOMMU (shared by both
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* PBMs of a controller, or per-PBM), and if a streaming buffer
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* is present, each PCI bus module has it's own. (ie. the IOMMU
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* might be shared between PBMs, the STC is never shared)
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* Furthermore, each PCI bus module controls it's own autonomous
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* PCI bus.
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*/
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struct pci_controller_info;
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/* This contains the software state necessary to drive a PCI
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* controller's IOMMU.
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*/
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struct pci_iommu_arena {
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unsigned long *map;
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unsigned int hint;
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unsigned int limit;
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};
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struct pci_iommu {
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/* This protects the controller's IOMMU and all
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* streaming buffers underneath.
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*/
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spinlock_t lock;
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struct pci_iommu_arena arena;
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/* IOMMU page table, a linear array of ioptes. */
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iopte_t *page_table; /* The page table itself. */
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/* Base PCI memory space address where IOMMU mappings
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* begin.
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*/
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u32 page_table_map_base;
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/* IOMMU Controller Registers */
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unsigned long iommu_control; /* IOMMU control register */
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unsigned long iommu_tsbbase; /* IOMMU page table base register */
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unsigned long iommu_flush; /* IOMMU page flush register */
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unsigned long iommu_ctxflush; /* IOMMU context flush register */
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/* This is a register in the PCI controller, which if
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* read will have no side-effects but will guarantee
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* completion of all previous writes into IOMMU/STC.
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*/
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unsigned long write_complete_reg;
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/* In order to deal with some buggy third-party PCI bridges that
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* do wrong prefetching, we never mark valid mappings as invalid.
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* Instead we point them at this dummy page.
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*/
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unsigned long dummy_page;
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unsigned long dummy_page_pa;
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/* CTX allocation. */
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unsigned long ctx_lowest_free;
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unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
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/* Here a PCI controller driver describes the areas of
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* PCI memory space where DMA to/from physical memory
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* are addressed. Drivers interrogate the PCI layer
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* if their device has addressing limitations. They
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* do so via pci_dma_supported, and pass in a mask of
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* DMA address bits their device can actually drive.
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*
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* The test for being usable is:
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* (device_mask & dma_addr_mask) == dma_addr_mask
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*/
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u32 dma_addr_mask;
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};
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extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
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/* This describes a PCI bus module's streaming buffer. */
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struct pci_strbuf {
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int strbuf_enabled; /* Present and using it? */
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/* Streaming Buffer Control Registers */
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unsigned long strbuf_control; /* STC control register */
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unsigned long strbuf_pflush; /* STC page flush register */
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unsigned long strbuf_fsync; /* STC flush synchronization reg */
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unsigned long strbuf_ctxflush; /* STC context flush register */
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unsigned long strbuf_ctxmatch_base; /* STC context flush match reg */
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unsigned long strbuf_flushflag_pa; /* Physical address of flush flag */
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volatile unsigned long *strbuf_flushflag; /* The flush flag itself */
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/* And this is the actual flush flag area.
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* We allocate extra because the chips require
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* a 64-byte aligned area.
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*/
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volatile unsigned long __flushflag_buf[(64 + (64 - 1)) / sizeof(long)];
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};
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#define PCI_STC_FLUSHFLAG_INIT(STC) \
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(*((STC)->strbuf_flushflag) = 0UL)
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#define PCI_STC_FLUSHFLAG_SET(STC) \
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(*((STC)->strbuf_flushflag) != 0UL)
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/* There can be quite a few ranges and interrupt maps on a PCI
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* segment. Thus...
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*/
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#define PROM_PCIRNG_MAX 64
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#define PROM_PCIIMAP_MAX 64
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struct pci_pbm_info {
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/* PCI controller we sit under. */
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struct pci_controller_info *parent;
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/* Physical address base of controller registers. */
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unsigned long controller_regs;
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/* Physical address base of PBM registers. */
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unsigned long pbm_regs;
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/* Physical address of DMA sync register, if any. */
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unsigned long sync_reg;
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/* Opaque 32-bit system bus Port ID. */
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u32 portid;
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/* Opaque 32-bit handle used for hypervisor calls. */
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u32 devhandle;
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/* Chipset version information. */
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int chip_type;
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#define PBM_CHIP_TYPE_SABRE 1
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#define PBM_CHIP_TYPE_PSYCHO 2
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#define PBM_CHIP_TYPE_SCHIZO 3
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#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
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#define PBM_CHIP_TYPE_TOMATILLO 5
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int chip_version;
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int chip_revision;
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/* Name used for top-level resources. */
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char *name;
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/* OBP specific information. */
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struct device_node *prom_node;
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struct linux_prom_pci_ranges *pbm_ranges;
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int num_pbm_ranges;
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struct linux_prom_pci_intmap *pbm_intmap;
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int num_pbm_intmap;
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struct linux_prom_pci_intmask *pbm_intmask;
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u64 ino_bitmap;
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/* PBM I/O and Memory space resources. */
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struct resource io_space;
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struct resource mem_space;
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/* Base of PCI Config space, can be per-PBM or shared. */
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unsigned long config_space;
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/* State of 66MHz capabilities on this PBM. */
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int is_66mhz_capable;
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int all_devs_66mhz;
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#ifdef CONFIG_PCI_MSI
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/* MSI info. */
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u32 msiq_num;
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u32 msiq_ent_count;
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u32 msiq_first;
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u32 msiq_first_devino;
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u32 msi_num;
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u32 msi_first;
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u32 msi_data_mask;
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u32 msix_data_width;
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u64 msi32_start;
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u64 msi64_start;
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u32 msi32_len;
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u32 msi64_len;
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void *msi_queues;
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unsigned long *msi_bitmap;
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#endif /* !(CONFIG_PCI_MSI) */
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/* This PBM's streaming buffer. */
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struct pci_strbuf stc;
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/* IOMMU state, potentially shared by both PBM segments. */
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struct pci_iommu *iommu;
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/* PCI slot mapping. */
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unsigned int pci_first_slot;
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/* Now things for the actual PCI bus probes. */
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unsigned int pci_first_busno;
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unsigned int pci_last_busno;
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struct pci_bus *pci_bus;
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};
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struct pci_controller_info {
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/* List of all PCI controllers. */
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struct pci_controller_info *next;
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/* Each controller gets a unique index, used mostly for
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* error logging purposes.
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*/
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int index;
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/* Do the PBMs both exist in the same PCI domain? */
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int pbms_same_domain;
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/* The PCI bus modules controlled by us. */
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struct pci_pbm_info pbm_A;
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struct pci_pbm_info pbm_B;
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/* Operations which are controller specific. */
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void (*scan_bus)(struct pci_controller_info *);
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void (*base_address_update)(struct pci_dev *, int);
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void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
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#ifdef CONFIG_PCI_MSI
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int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
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struct msi_desc *entry);
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void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
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#endif
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/* Now things for the actual PCI bus probes. */
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struct pci_ops *pci_ops;
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unsigned int pci_first_busno;
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unsigned int pci_last_busno;
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};
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/* PCI devices which are not bridges have this placed in their pci_dev
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* sysdata member. This makes OBP aware PCI device drivers easier to
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* code.
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*/
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struct pcidev_cookie {
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struct pci_pbm_info *pbm;
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struct device_node *prom_node;
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struct of_device *op;
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struct linux_prom_pci_registers prom_regs[PROMREG_MAX];
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int num_prom_regs;
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struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
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int num_prom_assignments;
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#ifdef CONFIG_PCI_MSI
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unsigned int msi_num;
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#endif
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};
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/* Currently these are the same across all PCI controllers
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* we support. Someday they may not be...
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*/
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#define PCI_IRQ_IGN 0x000007c0 /* Interrupt Group Number */
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#define PCI_IRQ_INO 0x0000003f /* Interrupt Number */
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#endif /* !(__SPARC64_PBM_H) */
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