mirror of https://gitee.com/openkylin/linux.git
96 lines
2.3 KiB
Plaintext
96 lines
2.3 KiB
Plaintext
#include <versatile-ab.dts>
|
|
|
|
/ {
|
|
model = "ARM Versatile PB";
|
|
compatible = "arm,versatile-pb";
|
|
|
|
amba {
|
|
gpio2: gpio@101e6000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x101e6000 0x1000>;
|
|
interrupts = <8>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pclk>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio3: gpio@101e7000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x101e7000 0x1000>;
|
|
interrupts = <9>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pclk>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
pci-controller@10001000 {
|
|
compatible = "arm,versatile-pci";
|
|
device_type = "pci";
|
|
reg = <0x10001000 0x1000
|
|
0x41000000 0x10000
|
|
0x42000000 0x100000>;
|
|
bus-range = <0 0xff>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
|
|
ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
|
|
0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
|
|
0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
|
|
|
|
interrupt-map-mask = <0x1800 0 0 7>;
|
|
interrupt-map = <0x1800 0 0 1 &sic 28
|
|
0x1800 0 0 2 &sic 29
|
|
0x1800 0 0 3 &sic 30
|
|
0x1800 0 0 4 &sic 27
|
|
|
|
0x1000 0 0 1 &sic 27
|
|
0x1000 0 0 2 &sic 28
|
|
0x1000 0 0 3 &sic 29
|
|
0x1000 0 0 4 &sic 30
|
|
|
|
0x0800 0 0 1 &sic 30
|
|
0x0800 0 0 2 &sic 27
|
|
0x0800 0 0 3 &sic 28
|
|
0x0800 0 0 4 &sic 29
|
|
|
|
0x0000 0 0 1 &sic 29
|
|
0x0000 0 0 2 &sic 30
|
|
0x0000 0 0 3 &sic 27
|
|
0x0000 0 0 4 &sic 28>;
|
|
};
|
|
|
|
fpga {
|
|
uart@9000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x9000 0x1000>;
|
|
interrupt-parent = <&sic>;
|
|
interrupts = <6>;
|
|
clocks = <&xtal24mhz>, <&pclk>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
};
|
|
sci@a000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0xa000 0x1000>;
|
|
interrupt-parent = <&sic>;
|
|
interrupts = <5>;
|
|
clocks = <&xtal24mhz>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
mmc@b000 {
|
|
compatible = "arm,pl180", "arm,primecell";
|
|
reg = <0xb000 0x1000>;
|
|
interrupts-extended = <&vic 23 &sic 2>;
|
|
clocks = <&xtal24mhz>, <&pclk>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
};
|
|
};
|
|
};
|
|
};
|