mirror of https://gitee.com/openkylin/linux.git
327 lines
11 KiB
C
327 lines
11 KiB
C
/*******************************************************************************
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STMMAC Common Header File
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/etherdevice.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
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#define STMMAC_VLAN_TAG_USED
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#include <linux/if_vlan.h>
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#endif
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#include "descs.h"
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#include "mmc.h"
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#undef CHIP_DEBUG_PRINT
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/* Turn-on extra printk debug for MAC core, dma and descriptors */
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/* #define CHIP_DEBUG_PRINT */
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#ifdef CHIP_DEBUG_PRINT
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#define CHIP_DBG(fmt, args...) printk(fmt, ## args)
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#else
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#define CHIP_DBG(fmt, args...) do { } while (0)
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#endif
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#undef FRAME_FILTER_DEBUG
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/* #define FRAME_FILTER_DEBUG */
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struct stmmac_extra_stats {
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/* Transmit errors */
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unsigned long tx_underflow ____cacheline_aligned;
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unsigned long tx_carrier;
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unsigned long tx_losscarrier;
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unsigned long vlan_tag;
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unsigned long tx_deferred;
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unsigned long tx_vlan;
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unsigned long tx_jabber;
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unsigned long tx_frame_flushed;
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unsigned long tx_payload_error;
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unsigned long tx_ip_header_error;
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/* Receive errors */
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unsigned long rx_desc;
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unsigned long sa_filter_fail;
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unsigned long overflow_error;
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unsigned long ipc_csum_error;
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unsigned long rx_collision;
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unsigned long rx_crc;
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unsigned long rx_length;
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unsigned long rx_mii;
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unsigned long rx_multicast;
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unsigned long rx_gmac_overflow;
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unsigned long rx_watchdog;
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unsigned long da_rx_filter_fail;
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unsigned long sa_rx_filter_fail;
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unsigned long rx_missed_cntr;
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unsigned long rx_overflow_cntr;
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unsigned long rx_vlan;
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/* Tx/Rx IRQ errors */
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unsigned long tx_undeflow_irq;
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unsigned long tx_process_stopped_irq;
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unsigned long tx_jabber_irq;
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unsigned long rx_overflow_irq;
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unsigned long rx_buf_unav_irq;
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unsigned long rx_process_stopped_irq;
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unsigned long rx_watchdog_irq;
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unsigned long tx_early_irq;
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unsigned long fatal_bus_error_irq;
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/* Extra info */
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unsigned long threshold;
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unsigned long tx_pkt_n;
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unsigned long rx_pkt_n;
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unsigned long poll_n;
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unsigned long sched_timer_n;
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unsigned long normal_irq_n;
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};
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#define HASH_TABLE_SIZE 64
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#define PAUSE_TIME 0x200
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/* Flow Control defines */
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#define FLOW_OFF 0
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#define FLOW_RX 1
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#define FLOW_TX 2
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#define FLOW_AUTO (FLOW_TX | FLOW_RX)
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#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
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/* DAM HW feature register fields */
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#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
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#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
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#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
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#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
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#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
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#define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */
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#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
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#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
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#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
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#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
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#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
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#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
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#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */
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#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */
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#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
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#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
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#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
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#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */
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#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */
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#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
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#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */
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#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */
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#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */
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#define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal
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System Time */
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#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
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#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
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#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
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enum rx_frame_status { /* IPC status */
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good_frame = 0,
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discard_frame = 1,
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csum_none = 2,
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llc_snap = 4,
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};
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enum tx_dma_irq_status {
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tx_hard_error = 1,
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tx_hard_error_bump_tc = 2,
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handle_tx_rx = 3,
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};
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/* DMA HW capabilities */
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struct dma_features {
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unsigned int mbps_10_100;
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unsigned int mbps_1000;
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unsigned int half_duplex;
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unsigned int hash_filter;
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unsigned int multi_addr;
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unsigned int pcs;
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unsigned int sma_mdio;
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unsigned int pmt_remote_wake_up;
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unsigned int pmt_magic_frame;
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unsigned int rmon;
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/* IEEE 1588-2002*/
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unsigned int time_stamp;
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/* IEEE 1588-2008*/
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unsigned int atime_stamp;
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/* 802.3az - Energy-Efficient Ethernet (EEE) */
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unsigned int eee;
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unsigned int av;
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/* TX and RX csum */
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unsigned int tx_coe;
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unsigned int rx_coe_type1;
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unsigned int rx_coe_type2;
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unsigned int rxfifo_over_2048;
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/* TX and RX number of channels */
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unsigned int number_rx_channel;
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unsigned int number_tx_channel;
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/* Alternate (enhanced) DESC mode*/
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unsigned int enh_desc;
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};
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/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
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#define BUF_SIZE_16KiB 16384
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#define BUF_SIZE_8KiB 8192
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#define BUF_SIZE_4KiB 4096
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#define BUF_SIZE_2KiB 2048
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/* Power Down and WOL */
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#define PMT_NOT_SUPPORTED 0
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#define PMT_SUPPORTED 1
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/* Common MAC defines */
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#define MAC_CTRL_REG 0x00000000 /* MAC Control */
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#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
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#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
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struct stmmac_desc_ops {
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/* DMA RX descriptor ring initialization */
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void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
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int disable_rx_ic);
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/* DMA TX descriptor ring initialization */
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void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
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/* Invoked by the xmit function to prepare the tx descriptor */
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void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
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int csum_flag);
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/* Set/get the owner of the descriptor */
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void (*set_tx_owner) (struct dma_desc *p);
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int (*get_tx_owner) (struct dma_desc *p);
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/* Invoked by the xmit function to close the tx descriptor */
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void (*close_tx_desc) (struct dma_desc *p);
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/* Clean the tx descriptor as soon as the tx irq is received */
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void (*release_tx_desc) (struct dma_desc *p);
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/* Clear interrupt on tx frame completion. When this bit is
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* set an interrupt happens as soon as the frame is transmitted */
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void (*clear_tx_ic) (struct dma_desc *p);
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/* Last tx segment reports the transmit status */
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int (*get_tx_ls) (struct dma_desc *p);
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/* Return the transmit status looking at the TDES1 */
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int (*tx_status) (void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p, void __iomem *ioaddr);
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/* Get the buffer size from the descriptor */
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int (*get_tx_len) (struct dma_desc *p);
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/* Handle extra events on specific interrupts hw dependent */
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int (*get_rx_owner) (struct dma_desc *p);
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void (*set_rx_owner) (struct dma_desc *p);
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/* Get the receive frame size */
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int (*get_rx_frame_len) (struct dma_desc *p);
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/* Return the reception status looking at the RDES1 */
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int (*rx_status) (void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p);
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};
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struct stmmac_dma_ops {
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/* DMA core initialization */
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int (*init) (void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
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/* Dump DMA registers */
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void (*dump_regs) (void __iomem *ioaddr);
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/* Set tx/rx threshold in the csr6 register
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* An invalid value enables the store-and-forward mode */
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void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
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/* To track extra statistic (if supported) */
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void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
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void __iomem *ioaddr);
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void (*enable_dma_transmission) (void __iomem *ioaddr);
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void (*enable_dma_irq) (void __iomem *ioaddr);
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void (*disable_dma_irq) (void __iomem *ioaddr);
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void (*start_tx) (void __iomem *ioaddr);
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void (*stop_tx) (void __iomem *ioaddr);
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void (*start_rx) (void __iomem *ioaddr);
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void (*stop_rx) (void __iomem *ioaddr);
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int (*dma_interrupt) (void __iomem *ioaddr,
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struct stmmac_extra_stats *x);
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/* If supported then get the optional core features */
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unsigned int (*get_hw_feature) (void __iomem *ioaddr);
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};
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struct stmmac_ops {
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/* MAC core initialization */
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void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
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/* Support checksum offload engine */
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int (*rx_coe) (void __iomem *ioaddr);
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/* Dump MAC registers */
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void (*dump_regs) (void __iomem *ioaddr);
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/* Handle extra events on specific interrupts hw dependent */
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void (*host_irq_status) (void __iomem *ioaddr);
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/* Multicast filter setting */
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void (*set_filter) (struct net_device *dev);
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/* Flow control setting */
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void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
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unsigned int fc, unsigned int pause_time);
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/* Set power management mode (e.g. magic frame) */
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void (*pmt) (void __iomem *ioaddr, unsigned long mode);
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/* Set/Get Unicast MAC addresses */
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void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
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unsigned int reg_n);
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void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
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unsigned int reg_n);
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};
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struct mac_link {
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int port;
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int duplex;
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int speed;
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};
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struct mii_regs {
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unsigned int addr; /* MII Address */
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unsigned int data; /* MII Data */
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};
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struct stmmac_ring_mode_ops {
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unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
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unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
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void (*refill_desc3) (int bfsize, struct dma_desc *p);
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void (*init_desc3) (int des3_as_data_buf, struct dma_desc *p);
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void (*init_dma_chain) (struct dma_desc *des, dma_addr_t phy_addr,
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unsigned int size);
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void (*clean_desc3) (struct dma_desc *p);
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int (*set_16kib_bfsize) (int mtu);
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};
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struct mac_device_info {
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const struct stmmac_ops *mac;
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const struct stmmac_desc_ops *desc;
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const struct stmmac_dma_ops *dma;
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const struct stmmac_ring_mode_ops *ring;
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struct mii_regs mii; /* MII register Addresses */
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struct mac_link link;
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unsigned int synopsys_uid;
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};
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struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
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struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
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extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
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unsigned int high, unsigned int low);
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extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int high, unsigned int low);
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extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);
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extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
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extern const struct stmmac_ring_mode_ops ring_mode_ops;
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