mirror of https://gitee.com/openkylin/linux.git
338 lines
9.5 KiB
C
338 lines
9.5 KiB
C
/*
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* Toshiba rbtx4927 specific setup
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* Copyright 2001-2002 MontaVista Software Inc.
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*
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* Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2000 RidgeRun, Inc.
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* Author: RidgeRun, Inc.
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* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* Copyright 2002 MontaVista Software Inc.
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* Author: Michael Pruznick, michael_pruznick@mvista.com
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* Copyright (C) 2004 MontaVista Software Inc.
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* Author: Manish Lachwani, mlachwani@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/reboot.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/pci.h>
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#include <asm/txx9/rbtx4927.h>
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#include <asm/txx9/tx4938.h> /* for TX4937 */
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#ifdef CONFIG_PCI
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static void __init tx4927_pci_setup(void)
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{
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int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
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struct pci_controller *c = &txx9_primary_pcic;
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register_pci_controller(c);
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if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
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txx9_pci_option =
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(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
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TXX9_PCI_OPT_CLK_66; /* already configured */
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/* Reset PCI Bus */
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writeb(1, rbtx4927_pcireset_addr);
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/* Reset PCIC */
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txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
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if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
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TXX9_PCI_OPT_CLK_66)
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tx4927_pciclk66_setup();
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mdelay(10);
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/* clear PCIC reset */
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txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
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writeb(0, rbtx4927_pcireset_addr);
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iob();
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tx4927_report_pciclk();
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tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
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if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
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TXX9_PCI_OPT_CLK_AUTO &&
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txx9_pci66_check(c, 0, 0)) {
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/* Reset PCI Bus */
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writeb(1, rbtx4927_pcireset_addr);
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/* Reset PCIC */
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txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
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tx4927_pciclk66_setup();
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mdelay(10);
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/* clear PCIC reset */
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txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
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writeb(0, rbtx4927_pcireset_addr);
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iob();
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/* Reinitialize PCIC */
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tx4927_report_pciclk();
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tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
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}
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tx4927_setup_pcierr_irq();
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}
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static void __init tx4937_pci_setup(void)
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{
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int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
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struct pci_controller *c = &txx9_primary_pcic;
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register_pci_controller(c);
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if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
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txx9_pci_option =
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(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
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TXX9_PCI_OPT_CLK_66; /* already configured */
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/* Reset PCI Bus */
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writeb(1, rbtx4927_pcireset_addr);
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/* Reset PCIC */
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txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
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if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
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TXX9_PCI_OPT_CLK_66)
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tx4938_pciclk66_setup();
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mdelay(10);
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/* clear PCIC reset */
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txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
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writeb(0, rbtx4927_pcireset_addr);
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iob();
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tx4938_report_pciclk();
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tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
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if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
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TXX9_PCI_OPT_CLK_AUTO &&
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txx9_pci66_check(c, 0, 0)) {
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/* Reset PCI Bus */
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writeb(1, rbtx4927_pcireset_addr);
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/* Reset PCIC */
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txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
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tx4938_pciclk66_setup();
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mdelay(10);
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/* clear PCIC reset */
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txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
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writeb(0, rbtx4927_pcireset_addr);
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iob();
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/* Reinitialize PCIC */
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tx4938_report_pciclk();
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tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
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}
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tx4938_setup_pcierr_irq();
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}
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static void __init rbtx4927_arch_init(void)
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{
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tx4927_pci_setup();
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}
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static void __init rbtx4937_arch_init(void)
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{
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tx4937_pci_setup();
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}
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#else
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#define rbtx4927_arch_init NULL
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#define rbtx4937_arch_init NULL
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#endif /* CONFIG_PCI */
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static void toshiba_rbtx4927_restart(char *command)
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{
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/* enable the s/w reset register */
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writeb(1, rbtx4927_softresetlock_addr);
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/* wait for enable to be seen */
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while (!(readb(rbtx4927_softresetlock_addr) & 1))
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;
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/* do a s/w reset */
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writeb(1, rbtx4927_softreset_addr);
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/* fallback */
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(*_machine_halt)();
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}
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static void __init rbtx4927_clock_init(void);
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static void __init rbtx4937_clock_init(void);
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static void __init rbtx4927_mem_setup(void)
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{
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u32 cp0_config;
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char *argptr;
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/* enable caches -- HCP5 does this, pmon does not */
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cp0_config = read_c0_config();
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cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
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write_c0_config(cp0_config);
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if (TX4927_REV_PCODE() == 0x4927) {
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rbtx4927_clock_init();
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tx4927_setup();
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} else {
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rbtx4937_clock_init();
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tx4938_setup();
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}
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_machine_restart = toshiba_rbtx4927_restart;
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#ifdef CONFIG_PCI
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txx9_alloc_pci_controller(&txx9_primary_pcic,
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RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
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RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
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txx9_board_pcibios_setup = tx4927_pcibios_setup;
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#else
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set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
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#endif
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tx4927_sio_init(0, 0);
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#ifdef CONFIG_SERIAL_TXX9_CONSOLE
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argptr = prom_getcmdline();
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if (!strstr(argptr, "console="))
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strcat(argptr, " console=ttyS0,38400");
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#endif
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}
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static void __init rbtx4927_clock_init(void)
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{
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/*
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* ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
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*
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* For TX4927:
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* PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
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* CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
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* CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
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* CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
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* CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
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* i.e. S9[3]: ON (83MHz), OFF (100MHz)
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*/
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switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
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TX4927_CCFG_PCIDIVMODE_MASK) {
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case TX4927_CCFG_PCIDIVMODE_2_5:
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case TX4927_CCFG_PCIDIVMODE_5:
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txx9_cpu_clock = 166666666; /* 166MHz */
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break;
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default:
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txx9_cpu_clock = 200000000; /* 200MHz */
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}
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}
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static void __init rbtx4937_clock_init(void)
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{
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/*
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* ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
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*
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* For TX4937:
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* PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
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* PCIDIVMODE[10] is 0.
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* CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
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* CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
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* CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
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* CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
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* CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
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* CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
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*/
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switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
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TX4938_CCFG_PCIDIVMODE_MASK) {
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case TX4938_CCFG_PCIDIVMODE_8:
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case TX4938_CCFG_PCIDIVMODE_4:
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txx9_cpu_clock = 266666666; /* 266MHz */
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break;
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case TX4938_CCFG_PCIDIVMODE_9:
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case TX4938_CCFG_PCIDIVMODE_4_5:
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txx9_cpu_clock = 300000000; /* 300MHz */
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break;
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default:
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txx9_cpu_clock = 333333333; /* 333MHz */
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}
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}
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static void __init rbtx4927_time_init(void)
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{
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tx4927_time_init(0);
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}
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static void __init toshiba_rbtx4927_rtc_init(void)
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{
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struct resource res = {
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.start = RBTX4927_BRAMRTC_BASE - IO_BASE,
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.end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
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.flags = IORESOURCE_MEM,
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};
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platform_device_register_simple("rtc-ds1742", -1, &res, 1);
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}
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static void __init rbtx4927_ne_init(void)
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{
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struct resource res[] = {
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{
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.start = RBTX4927_RTL_8019_BASE,
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.end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
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.flags = IORESOURCE_IO,
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}, {
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.start = RBTX4927_RTL_8019_IRQ,
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.flags = IORESOURCE_IRQ,
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}
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};
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platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
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}
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static void __init rbtx4927_device_init(void)
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{
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toshiba_rbtx4927_rtc_init();
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rbtx4927_ne_init();
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tx4927_wdt_init();
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}
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struct txx9_board_vec rbtx4927_vec __initdata = {
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.system = "Toshiba RBTX4927",
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.prom_init = rbtx4927_prom_init,
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.mem_setup = rbtx4927_mem_setup,
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.irq_setup = rbtx4927_irq_setup,
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.time_init = rbtx4927_time_init,
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.device_init = rbtx4927_device_init,
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.arch_init = rbtx4927_arch_init,
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#ifdef CONFIG_PCI
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.pci_map_irq = rbtx4927_pci_map_irq,
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#endif
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};
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struct txx9_board_vec rbtx4937_vec __initdata = {
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.system = "Toshiba RBTX4937",
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.prom_init = rbtx4927_prom_init,
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.mem_setup = rbtx4927_mem_setup,
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.irq_setup = rbtx4927_irq_setup,
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.time_init = rbtx4927_time_init,
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.device_init = rbtx4927_device_init,
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.arch_init = rbtx4937_arch_init,
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#ifdef CONFIG_PCI
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.pci_map_irq = rbtx4927_pci_map_irq,
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#endif
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};
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