mirror of https://gitee.com/openkylin/linux.git
498 lines
12 KiB
C
498 lines
12 KiB
C
/****************************************************************************/
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/*
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* nettel.c -- mappings for NETtel/SecureEdge/SnapGear (x86) boards.
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*
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* (C) Copyright 2000-2001, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2001-2002, SnapGear (www.snapgear.com)
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*
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* $Id: nettel.c,v 1.12 2005/11/29 14:30:00 gleixner Exp $
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*/
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/****************************************************************************/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/cfi.h>
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#include <linux/reboot.h>
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#include <linux/kdev_t.h>
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#include <linux/root_dev.h>
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#include <asm/io.h>
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/****************************************************************************/
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#define INTEL_BUSWIDTH 1
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#define AMD_WINDOW_MAXSIZE 0x00200000
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#define AMD_BUSWIDTH 1
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/*
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* PAR masks and shifts, assuming 64K pages.
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*/
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#define SC520_PAR_ADDR_MASK 0x00003fff
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#define SC520_PAR_ADDR_SHIFT 16
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#define SC520_PAR_TO_ADDR(par) \
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(((par)&SC520_PAR_ADDR_MASK) << SC520_PAR_ADDR_SHIFT)
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#define SC520_PAR_SIZE_MASK 0x01ffc000
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#define SC520_PAR_SIZE_SHIFT 2
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#define SC520_PAR_TO_SIZE(par) \
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((((par)&SC520_PAR_SIZE_MASK) << SC520_PAR_SIZE_SHIFT) + (64*1024))
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#define SC520_PAR(cs, addr, size) \
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((cs) | \
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((((size)-(64*1024)) >> SC520_PAR_SIZE_SHIFT) & SC520_PAR_SIZE_MASK) | \
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(((addr) >> SC520_PAR_ADDR_SHIFT) & SC520_PAR_ADDR_MASK))
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#define SC520_PAR_BOOTCS 0x8a000000
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#define SC520_PAR_ROMCS1 0xaa000000
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#define SC520_PAR_ROMCS2 0xca000000 /* Cache disabled, 64K page */
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static void *nettel_mmcrp = NULL;
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#ifdef CONFIG_MTD_CFI_INTELEXT
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static struct mtd_info *intel_mtd;
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#endif
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static struct mtd_info *amd_mtd;
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/****************************************************************************/
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/****************************************************************************/
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#ifdef CONFIG_MTD_CFI_INTELEXT
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static struct map_info nettel_intel_map = {
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.name = "SnapGear Intel",
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.size = 0,
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.bankwidth = INTEL_BUSWIDTH,
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};
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static struct mtd_partition nettel_intel_partitions[] = {
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{
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.name = "SnapGear kernel",
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.offset = 0,
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.size = 0x000e0000
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},
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{
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.name = "SnapGear filesystem",
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.offset = 0x00100000,
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},
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{
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.name = "SnapGear config",
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.offset = 0x000e0000,
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.size = 0x00020000
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},
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{
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.name = "SnapGear Intel",
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.offset = 0
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},
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{
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.name = "SnapGear BIOS Config",
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.offset = 0x007e0000,
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.size = 0x00020000
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},
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{
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.name = "SnapGear BIOS",
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.offset = 0x007e0000,
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.size = 0x00020000
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},
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};
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#endif
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static struct map_info nettel_amd_map = {
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.name = "SnapGear AMD",
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.size = AMD_WINDOW_MAXSIZE,
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.bankwidth = AMD_BUSWIDTH,
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};
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static struct mtd_partition nettel_amd_partitions[] = {
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{
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.name = "SnapGear BIOS config",
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.offset = 0x000e0000,
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.size = 0x00010000
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},
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{
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.name = "SnapGear BIOS",
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.offset = 0x000f0000,
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.size = 0x00010000
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},
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{
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.name = "SnapGear AMD",
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.offset = 0
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},
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{
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.name = "SnapGear high BIOS",
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.offset = 0x001f0000,
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.size = 0x00010000
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}
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};
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#define NUM_AMD_PARTITIONS ARRAY_SIZE(nettel_amd_partitions)
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/****************************************************************************/
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#ifdef CONFIG_MTD_CFI_INTELEXT
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/*
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* Set the Intel flash back to read mode since some old boot
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* loaders don't.
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*/
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static int nettel_reboot_notifier(struct notifier_block *nb, unsigned long val, void *v)
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{
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struct cfi_private *cfi = nettel_intel_map.fldrv_priv;
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unsigned long b;
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/* Make sure all FLASH chips are put back into read mode */
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for (b = 0; (b < nettel_intel_partitions[3].size); b += 0x100000) {
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cfi_send_gen_cmd(0xff, 0x55, b, &nettel_intel_map, cfi,
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cfi->device_type, NULL);
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}
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return(NOTIFY_OK);
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}
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static struct notifier_block nettel_notifier_block = {
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nettel_reboot_notifier, NULL, 0
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};
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/*
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* Erase the configuration file system.
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* Used to support the software reset button.
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*/
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static void nettel_erasecallback(struct erase_info *done)
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{
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wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
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wake_up(wait_q);
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}
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static struct erase_info nettel_erase;
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int nettel_eraseconfig(void)
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{
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struct mtd_info *mtd;
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DECLARE_WAITQUEUE(wait, current);
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wait_queue_head_t wait_q;
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int ret;
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init_waitqueue_head(&wait_q);
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mtd = get_mtd_device(NULL, 2);
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if (mtd) {
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nettel_erase.mtd = mtd;
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nettel_erase.callback = nettel_erasecallback;
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nettel_erase.callback = NULL;
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nettel_erase.addr = 0;
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nettel_erase.len = mtd->size;
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nettel_erase.priv = (u_long) &wait_q;
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nettel_erase.priv = 0;
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set_current_state(TASK_INTERRUPTIBLE);
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add_wait_queue(&wait_q, &wait);
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ret = mtd->erase(mtd, &nettel_erase);
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if (ret) {
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set_current_state(TASK_RUNNING);
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remove_wait_queue(&wait_q, &wait);
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put_mtd_device(mtd);
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return(ret);
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}
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schedule(); /* Wait for erase to finish. */
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remove_wait_queue(&wait_q, &wait);
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put_mtd_device(mtd);
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}
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return(0);
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}
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#else
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int nettel_eraseconfig(void)
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{
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return(0);
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}
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#endif
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/****************************************************************************/
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int __init nettel_init(void)
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{
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volatile unsigned long *amdpar;
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unsigned long amdaddr, maxsize;
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int num_amd_partitions=0;
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#ifdef CONFIG_MTD_CFI_INTELEXT
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volatile unsigned long *intel0par, *intel1par;
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unsigned long orig_bootcspar, orig_romcs1par;
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unsigned long intel0addr, intel0size;
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unsigned long intel1addr, intel1size;
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int intelboot, intel0cs, intel1cs;
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int num_intel_partitions;
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#endif
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int rc = 0;
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nettel_mmcrp = (void *) ioremap_nocache(0xfffef000, 4096);
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if (nettel_mmcrp == NULL) {
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printk("SNAPGEAR: failed to disable MMCR cache??\n");
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return(-EIO);
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}
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/* Set CPU clock to be 33.000MHz */
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*((unsigned char *) (nettel_mmcrp + 0xc64)) = 0x01;
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amdpar = (volatile unsigned long *) (nettel_mmcrp + 0xc4);
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#ifdef CONFIG_MTD_CFI_INTELEXT
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intelboot = 0;
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intel0cs = SC520_PAR_ROMCS1;
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intel0par = (volatile unsigned long *) (nettel_mmcrp + 0xc0);
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intel1cs = SC520_PAR_ROMCS2;
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intel1par = (volatile unsigned long *) (nettel_mmcrp + 0xbc);
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/*
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* Save the CS settings then ensure ROMCS1 and ROMCS2 are off,
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* otherwise they might clash with where we try to map BOOTCS.
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*/
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orig_bootcspar = *amdpar;
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orig_romcs1par = *intel0par;
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*intel0par = 0;
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*intel1par = 0;
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#endif
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/*
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* The first thing to do is determine if we have a separate
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* boot FLASH device. Typically this is a small (1 to 2MB)
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* AMD FLASH part. It seems that device size is about the
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* only way to tell if this is the case...
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*/
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amdaddr = 0x20000000;
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maxsize = AMD_WINDOW_MAXSIZE;
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*amdpar = SC520_PAR(SC520_PAR_BOOTCS, amdaddr, maxsize);
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__asm__ ("wbinvd");
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nettel_amd_map.phys = amdaddr;
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nettel_amd_map.virt = ioremap_nocache(amdaddr, maxsize);
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if (!nettel_amd_map.virt) {
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printk("SNAPGEAR: failed to ioremap() BOOTCS\n");
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return(-EIO);
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}
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simple_map_init(&nettel_amd_map);
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if ((amd_mtd = do_map_probe("jedec_probe", &nettel_amd_map))) {
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printk(KERN_NOTICE "SNAPGEAR: AMD flash device size = %dK\n",
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amd_mtd->size>>10);
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amd_mtd->owner = THIS_MODULE;
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/* The high BIOS partition is only present for 2MB units */
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num_amd_partitions = NUM_AMD_PARTITIONS;
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if (amd_mtd->size < AMD_WINDOW_MAXSIZE)
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num_amd_partitions--;
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/* Don't add the partition until after the primary INTEL's */
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#ifdef CONFIG_MTD_CFI_INTELEXT
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/*
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* Map the Intel flash into memory after the AMD
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* It has to start on a multiple of maxsize.
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*/
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maxsize = SC520_PAR_TO_SIZE(orig_romcs1par);
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if (maxsize < (32 * 1024 * 1024))
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maxsize = (32 * 1024 * 1024);
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intel0addr = amdaddr + maxsize;
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#endif
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} else {
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#ifdef CONFIG_MTD_CFI_INTELEXT
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/* INTEL boot FLASH */
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intelboot++;
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if (!orig_romcs1par) {
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intel0cs = SC520_PAR_BOOTCS;
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intel0par = (volatile unsigned long *)
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(nettel_mmcrp + 0xc4);
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intel1cs = SC520_PAR_ROMCS1;
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intel1par = (volatile unsigned long *)
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(nettel_mmcrp + 0xc0);
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intel0addr = SC520_PAR_TO_ADDR(orig_bootcspar);
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maxsize = SC520_PAR_TO_SIZE(orig_bootcspar);
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} else {
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/* Kernel base is on ROMCS1, not BOOTCS */
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intel0cs = SC520_PAR_ROMCS1;
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intel0par = (volatile unsigned long *)
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(nettel_mmcrp + 0xc0);
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intel1cs = SC520_PAR_BOOTCS;
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intel1par = (volatile unsigned long *)
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(nettel_mmcrp + 0xc4);
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intel0addr = SC520_PAR_TO_ADDR(orig_romcs1par);
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maxsize = SC520_PAR_TO_SIZE(orig_romcs1par);
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}
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/* Destroy useless AMD MTD mapping */
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amd_mtd = NULL;
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iounmap(nettel_amd_map.virt);
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nettel_amd_map.virt = NULL;
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#else
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/* Only AMD flash supported */
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return(-ENXIO);
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#endif
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}
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#ifdef CONFIG_MTD_CFI_INTELEXT
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/*
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* We have determined the INTEL FLASH configuration, so lets
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* go ahead and probe for them now.
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*/
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/* Set PAR to the maximum size */
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if (maxsize < (32 * 1024 * 1024))
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maxsize = (32 * 1024 * 1024);
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*intel0par = SC520_PAR(intel0cs, intel0addr, maxsize);
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/* Turn other PAR off so the first probe doesn't find it */
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*intel1par = 0;
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/* Probe for the the size of the first Intel flash */
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nettel_intel_map.size = maxsize;
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nettel_intel_map.phys = intel0addr;
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nettel_intel_map.virt = ioremap_nocache(intel0addr, maxsize);
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if (!nettel_intel_map.virt) {
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printk("SNAPGEAR: failed to ioremap() ROMCS1\n");
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return(-EIO);
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}
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simple_map_init(&nettel_intel_map);
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intel_mtd = do_map_probe("cfi_probe", &nettel_intel_map);
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if (!intel_mtd) {
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iounmap(nettel_intel_map.virt);
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return(-ENXIO);
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}
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/* Set PAR to the detected size */
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intel0size = intel_mtd->size;
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*intel0par = SC520_PAR(intel0cs, intel0addr, intel0size);
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/*
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* Map second Intel FLASH right after first. Set its size to the
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* same maxsize used for the first Intel FLASH.
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*/
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intel1addr = intel0addr + intel0size;
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*intel1par = SC520_PAR(intel1cs, intel1addr, maxsize);
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__asm__ ("wbinvd");
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maxsize += intel0size;
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/* Delete the old map and probe again to do both chips */
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map_destroy(intel_mtd);
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intel_mtd = NULL;
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iounmap(nettel_intel_map.virt);
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nettel_intel_map.size = maxsize;
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nettel_intel_map.virt = ioremap_nocache(intel0addr, maxsize);
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if (!nettel_intel_map.virt) {
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printk("SNAPGEAR: failed to ioremap() ROMCS1/2\n");
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return(-EIO);
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}
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intel_mtd = do_map_probe("cfi_probe", &nettel_intel_map);
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if (! intel_mtd) {
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iounmap((void *) nettel_intel_map.virt);
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return(-ENXIO);
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}
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intel1size = intel_mtd->size - intel0size;
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if (intel1size > 0) {
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*intel1par = SC520_PAR(intel1cs, intel1addr, intel1size);
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__asm__ ("wbinvd");
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} else {
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*intel1par = 0;
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}
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printk(KERN_NOTICE "SNAPGEAR: Intel flash device size = %dK\n",
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(intel_mtd->size >> 10));
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intel_mtd->owner = THIS_MODULE;
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#ifndef CONFIG_BLK_DEV_INITRD
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ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 1);
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#endif
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num_intel_partitions = sizeof(nettel_intel_partitions) /
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sizeof(nettel_intel_partitions[0]);
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if (intelboot) {
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/*
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* Adjust offset and size of last boot partition.
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* Must allow for BIOS region at end of FLASH.
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*/
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nettel_intel_partitions[1].size = (intel0size + intel1size) -
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(1024*1024 + intel_mtd->erasesize);
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nettel_intel_partitions[3].size = intel0size + intel1size;
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nettel_intel_partitions[4].offset =
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(intel0size + intel1size) - intel_mtd->erasesize;
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nettel_intel_partitions[4].size = intel_mtd->erasesize;
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nettel_intel_partitions[5].offset =
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nettel_intel_partitions[4].offset;
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nettel_intel_partitions[5].size =
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nettel_intel_partitions[4].size;
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} else {
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/* No BIOS regions when AMD boot */
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num_intel_partitions -= 2;
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}
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rc = add_mtd_partitions(intel_mtd, nettel_intel_partitions,
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num_intel_partitions);
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#endif
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if (amd_mtd) {
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rc = add_mtd_partitions(amd_mtd, nettel_amd_partitions,
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num_amd_partitions);
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}
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#ifdef CONFIG_MTD_CFI_INTELEXT
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register_reboot_notifier(&nettel_notifier_block);
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#endif
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return(rc);
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}
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/****************************************************************************/
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void __exit nettel_cleanup(void)
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{
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#ifdef CONFIG_MTD_CFI_INTELEXT
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unregister_reboot_notifier(&nettel_notifier_block);
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#endif
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if (amd_mtd) {
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del_mtd_partitions(amd_mtd);
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map_destroy(amd_mtd);
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}
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if (nettel_amd_map.virt) {
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iounmap(nettel_amd_map.virt);
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nettel_amd_map.virt = NULL;
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}
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#ifdef CONFIG_MTD_CFI_INTELEXT
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if (intel_mtd) {
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del_mtd_partitions(intel_mtd);
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map_destroy(intel_mtd);
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}
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if (nettel_intel_map.virt) {
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iounmap(nettel_intel_map.virt);
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nettel_intel_map.virt = NULL;
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}
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#endif
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}
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/****************************************************************************/
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module_init(nettel_init);
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module_exit(nettel_cleanup);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
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MODULE_DESCRIPTION("SnapGear/SecureEdge FLASH support");
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/****************************************************************************/
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