mirror of https://gitee.com/openkylin/linux.git
878 lines
22 KiB
C
878 lines
22 KiB
C
/*
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* arch/arm/mach-omap2/serial.c
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*
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* OMAP2 serial support.
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*
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* Copyright (C) 2005-2008 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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*
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* Major rework for PM support by Kevin Hilman
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*
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* Based off of arch/arm/mach-omap/omap1/serial.c
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/serial_reg.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/serial_8250.h>
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#include <linux/pm_runtime.h>
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#include <linux/console.h>
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#ifdef CONFIG_SERIAL_OMAP
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#include <plat/omap-serial.h>
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#endif
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#include <plat/common.h>
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#include <plat/board.h>
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#include <plat/clock.h>
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#include <plat/dma.h>
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#include <plat/omap_hwmod.h>
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#include <plat/omap_device.h>
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#include "prm2xxx_3xxx.h"
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#include "pm.h"
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#include "cm2xxx_3xxx.h"
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#include "prm-regbits-34xx.h"
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#include "control.h"
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#include "mux.h"
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#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
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#define UART_OMAP_WER 0x17 /* Wake-up enable register */
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#define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0)
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#define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
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/*
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* NOTE: By default the serial timeout is disabled as it causes lost characters
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* over the serial ports. This means that the UART clocks will stay on until
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* disabled via sysfs. This also causes that any deeper omap sleep states are
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* blocked.
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*/
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#define DEFAULT_TIMEOUT 0
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#define MAX_UART_HWMOD_NAME_LEN 16
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struct omap_uart_state {
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int num;
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int can_sleep;
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struct timer_list timer;
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u32 timeout;
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void __iomem *wk_st;
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void __iomem *wk_en;
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u32 wk_mask;
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u32 padconf;
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u32 dma_enabled;
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struct clk *ick;
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struct clk *fck;
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int clocked;
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int irq;
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int regshift;
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int irqflags;
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void __iomem *membase;
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resource_size_t mapbase;
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struct list_head node;
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struct omap_hwmod *oh;
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struct platform_device *pdev;
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u32 errata;
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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int context_valid;
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/* Registers to be saved/restored for OFF-mode */
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u16 dll;
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u16 dlh;
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u16 ier;
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u16 sysc;
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u16 scr;
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u16 wer;
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u16 mcr;
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#endif
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};
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static LIST_HEAD(uart_list);
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static u8 num_uarts;
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static int uart_idle_hwmod(struct omap_device *od)
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{
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omap_hwmod_idle(od->hwmods[0]);
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return 0;
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}
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static int uart_enable_hwmod(struct omap_device *od)
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{
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omap_hwmod_enable(od->hwmods[0]);
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return 0;
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}
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static struct omap_device_pm_latency omap_uart_latency[] = {
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{
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.deactivate_func = uart_idle_hwmod,
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.activate_func = uart_enable_hwmod,
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.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
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},
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};
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static inline unsigned int __serial_read_reg(struct uart_port *up,
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int offset)
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{
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offset <<= up->regshift;
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return (unsigned int)__raw_readb(up->membase + offset);
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}
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static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
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int offset)
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{
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offset <<= uart->regshift;
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return (unsigned int)__raw_readb(uart->membase + offset);
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}
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static inline void __serial_write_reg(struct uart_port *up, int offset,
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int value)
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{
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offset <<= up->regshift;
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__raw_writeb(value, up->membase + offset);
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}
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static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
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int value)
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{
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offset <<= uart->regshift;
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__raw_writeb(value, uart->membase + offset);
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}
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/*
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* Internal UARTs need to be initialized for the 8250 autoconfig to work
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* properly. Note that the TX watermark initialization may not be needed
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* once the 8250.c watermark handling code is merged.
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*/
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static inline void __init omap_uart_reset(struct omap_uart_state *uart)
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{
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serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
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serial_write_reg(uart, UART_OMAP_SCR, 0x08);
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serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
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}
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#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
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/*
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* Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
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* The access to uart register after MDR1 Access
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* causes UART to corrupt data.
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*
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* Need a delay =
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* 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
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* give 10 times as much
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*/
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static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
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u8 fcr_val)
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{
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u8 timeout = 255;
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serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
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udelay(2);
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serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
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UART_FCR_CLEAR_RCVR);
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/*
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* Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
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* TX_FIFO_E bit is 1.
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*/
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while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
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(UART_LSR_THRE | UART_LSR_DR))) {
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timeout--;
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if (!timeout) {
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/* Should *never* happen. we warn and carry on */
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dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
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serial_read_reg(uart, UART_LSR));
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break;
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}
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udelay(1);
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}
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}
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static void omap_uart_save_context(struct omap_uart_state *uart)
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{
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u16 lcr = 0;
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if (!enable_off_mode)
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return;
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lcr = serial_read_reg(uart, UART_LCR);
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serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
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uart->dll = serial_read_reg(uart, UART_DLL);
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uart->dlh = serial_read_reg(uart, UART_DLM);
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serial_write_reg(uart, UART_LCR, lcr);
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uart->ier = serial_read_reg(uart, UART_IER);
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uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
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uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
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uart->wer = serial_read_reg(uart, UART_OMAP_WER);
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serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
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uart->mcr = serial_read_reg(uart, UART_MCR);
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serial_write_reg(uart, UART_LCR, lcr);
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uart->context_valid = 1;
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}
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static void omap_uart_restore_context(struct omap_uart_state *uart)
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{
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u16 efr = 0;
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if (!enable_off_mode)
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return;
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if (!uart->context_valid)
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return;
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uart->context_valid = 0;
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if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
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omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
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else
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serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
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serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
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efr = serial_read_reg(uart, UART_EFR);
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serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
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serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
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serial_write_reg(uart, UART_IER, 0x0);
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serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
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serial_write_reg(uart, UART_DLL, uart->dll);
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serial_write_reg(uart, UART_DLM, uart->dlh);
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serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
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serial_write_reg(uart, UART_IER, uart->ier);
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serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
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serial_write_reg(uart, UART_MCR, uart->mcr);
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serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
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serial_write_reg(uart, UART_EFR, efr);
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serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
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serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
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serial_write_reg(uart, UART_OMAP_WER, uart->wer);
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serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
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if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
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omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
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else
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/* UART 16x mode */
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serial_write_reg(uart, UART_OMAP_MDR1,
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UART_OMAP_MDR1_16X_MODE);
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}
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#else
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static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
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static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
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#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
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static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
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{
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if (uart->clocked)
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return;
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omap_device_enable(uart->pdev);
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uart->clocked = 1;
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omap_uart_restore_context(uart);
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}
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#ifdef CONFIG_PM
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static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
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{
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if (!uart->clocked)
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return;
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omap_uart_save_context(uart);
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uart->clocked = 0;
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omap_device_idle(uart->pdev);
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}
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static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
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{
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/* Set wake-enable bit */
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if (uart->wk_en && uart->wk_mask) {
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u32 v = __raw_readl(uart->wk_en);
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v |= uart->wk_mask;
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__raw_writel(v, uart->wk_en);
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}
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/* Ensure IOPAD wake-enables are set */
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if (cpu_is_omap34xx() && uart->padconf) {
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u16 v = omap_ctrl_readw(uart->padconf);
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v |= OMAP3_PADCONF_WAKEUPENABLE0;
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omap_ctrl_writew(v, uart->padconf);
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}
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}
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static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
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{
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/* Clear wake-enable bit */
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if (uart->wk_en && uart->wk_mask) {
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u32 v = __raw_readl(uart->wk_en);
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v &= ~uart->wk_mask;
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__raw_writel(v, uart->wk_en);
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}
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/* Ensure IOPAD wake-enables are cleared */
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if (cpu_is_omap34xx() && uart->padconf) {
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u16 v = omap_ctrl_readw(uart->padconf);
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v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
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omap_ctrl_writew(v, uart->padconf);
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}
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}
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static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
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int enable)
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{
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u8 idlemode;
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if (enable) {
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/**
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* Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
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* in Smartidle Mode When Configured for DMA Operations.
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*/
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if (uart->dma_enabled)
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idlemode = HWMOD_IDLEMODE_FORCE;
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else
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idlemode = HWMOD_IDLEMODE_SMART;
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} else {
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idlemode = HWMOD_IDLEMODE_NO;
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}
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omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
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}
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static void omap_uart_block_sleep(struct omap_uart_state *uart)
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{
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omap_uart_enable_clocks(uart);
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omap_uart_smart_idle_enable(uart, 0);
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uart->can_sleep = 0;
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if (uart->timeout)
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mod_timer(&uart->timer, jiffies + uart->timeout);
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else
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del_timer(&uart->timer);
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}
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static void omap_uart_allow_sleep(struct omap_uart_state *uart)
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{
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if (device_may_wakeup(&uart->pdev->dev))
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omap_uart_enable_wakeup(uart);
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else
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omap_uart_disable_wakeup(uart);
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if (!uart->clocked)
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return;
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omap_uart_smart_idle_enable(uart, 1);
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uart->can_sleep = 1;
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del_timer(&uart->timer);
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}
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static void omap_uart_idle_timer(unsigned long data)
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{
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struct omap_uart_state *uart = (struct omap_uart_state *)data;
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omap_uart_allow_sleep(uart);
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}
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void omap_uart_prepare_idle(int num)
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{
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struct omap_uart_state *uart;
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list_for_each_entry(uart, &uart_list, node) {
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if (num == uart->num && uart->can_sleep) {
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omap_uart_disable_clocks(uart);
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return;
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}
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}
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}
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void omap_uart_resume_idle(int num)
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{
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struct omap_uart_state *uart;
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list_for_each_entry(uart, &uart_list, node) {
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if (num == uart->num && uart->can_sleep) {
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omap_uart_enable_clocks(uart);
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/* Check for IO pad wakeup */
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if (cpu_is_omap34xx() && uart->padconf) {
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u16 p = omap_ctrl_readw(uart->padconf);
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if (p & OMAP3_PADCONF_WAKEUPEVENT0)
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omap_uart_block_sleep(uart);
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}
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/* Check for normal UART wakeup */
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if (__raw_readl(uart->wk_st) & uart->wk_mask)
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omap_uart_block_sleep(uart);
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return;
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}
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}
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}
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void omap_uart_prepare_suspend(void)
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{
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struct omap_uart_state *uart;
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list_for_each_entry(uart, &uart_list, node) {
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omap_uart_allow_sleep(uart);
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}
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}
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int omap_uart_can_sleep(void)
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{
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struct omap_uart_state *uart;
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int can_sleep = 1;
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list_for_each_entry(uart, &uart_list, node) {
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if (!uart->clocked)
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continue;
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if (!uart->can_sleep) {
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can_sleep = 0;
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continue;
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}
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/* This UART can now safely sleep. */
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omap_uart_allow_sleep(uart);
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}
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return can_sleep;
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}
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/**
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* omap_uart_interrupt()
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*
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* This handler is used only to detect that *any* UART interrupt has
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* occurred. It does _nothing_ to handle the interrupt. Rather,
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* any UART interrupt will trigger the inactivity timer so the
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* UART will not idle or sleep for its timeout period.
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*
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**/
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/* static int first_interrupt; */
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static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
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{
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struct omap_uart_state *uart = dev_id;
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omap_uart_block_sleep(uart);
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return IRQ_NONE;
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}
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static void omap_uart_idle_init(struct omap_uart_state *uart)
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{
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int ret;
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uart->can_sleep = 0;
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uart->timeout = DEFAULT_TIMEOUT;
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setup_timer(&uart->timer, omap_uart_idle_timer,
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(unsigned long) uart);
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if (uart->timeout)
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mod_timer(&uart->timer, jiffies + uart->timeout);
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omap_uart_smart_idle_enable(uart, 0);
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if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
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u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
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u32 wk_mask = 0;
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u32 padconf = 0;
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/* XXX These PRM accesses do not belong here */
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uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
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uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
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|
switch (uart->num) {
|
|
case 0:
|
|
wk_mask = OMAP3430_ST_UART1_MASK;
|
|
padconf = 0x182;
|
|
break;
|
|
case 1:
|
|
wk_mask = OMAP3430_ST_UART2_MASK;
|
|
padconf = 0x17a;
|
|
break;
|
|
case 2:
|
|
wk_mask = OMAP3430_ST_UART3_MASK;
|
|
padconf = 0x19e;
|
|
break;
|
|
case 3:
|
|
wk_mask = OMAP3630_ST_UART4_MASK;
|
|
padconf = 0x0d2;
|
|
break;
|
|
}
|
|
uart->wk_mask = wk_mask;
|
|
uart->padconf = padconf;
|
|
} else if (cpu_is_omap24xx()) {
|
|
u32 wk_mask = 0;
|
|
u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
|
|
|
|
switch (uart->num) {
|
|
case 0:
|
|
wk_mask = OMAP24XX_ST_UART1_MASK;
|
|
break;
|
|
case 1:
|
|
wk_mask = OMAP24XX_ST_UART2_MASK;
|
|
break;
|
|
case 2:
|
|
wk_en = OMAP24XX_PM_WKEN2;
|
|
wk_st = OMAP24XX_PM_WKST2;
|
|
wk_mask = OMAP24XX_ST_UART3_MASK;
|
|
break;
|
|
}
|
|
uart->wk_mask = wk_mask;
|
|
if (cpu_is_omap2430()) {
|
|
uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
|
|
uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
|
|
} else if (cpu_is_omap2420()) {
|
|
uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
|
|
uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
|
|
}
|
|
} else {
|
|
uart->wk_en = NULL;
|
|
uart->wk_st = NULL;
|
|
uart->wk_mask = 0;
|
|
uart->padconf = 0;
|
|
}
|
|
|
|
uart->irqflags |= IRQF_SHARED;
|
|
ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
|
|
IRQF_SHARED, "serial idle", (void *)uart);
|
|
WARN_ON(ret);
|
|
}
|
|
|
|
void omap_uart_enable_irqs(int enable)
|
|
{
|
|
int ret;
|
|
struct omap_uart_state *uart;
|
|
|
|
list_for_each_entry(uart, &uart_list, node) {
|
|
if (enable) {
|
|
pm_runtime_put_sync(&uart->pdev->dev);
|
|
ret = request_threaded_irq(uart->irq, NULL,
|
|
omap_uart_interrupt,
|
|
IRQF_SHARED,
|
|
"serial idle",
|
|
(void *)uart);
|
|
} else {
|
|
pm_runtime_get_noresume(&uart->pdev->dev);
|
|
free_irq(uart->irq, (void *)uart);
|
|
}
|
|
}
|
|
}
|
|
|
|
static ssize_t sleep_timeout_show(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct omap_device *odev = to_omap_device(pdev);
|
|
struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
|
|
|
|
return sprintf(buf, "%u\n", uart->timeout / HZ);
|
|
}
|
|
|
|
static ssize_t sleep_timeout_store(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf, size_t n)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct omap_device *odev = to_omap_device(pdev);
|
|
struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
|
|
unsigned int value;
|
|
|
|
if (sscanf(buf, "%u", &value) != 1) {
|
|
dev_err(dev, "sleep_timeout_store: Invalid value\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
uart->timeout = value * HZ;
|
|
if (uart->timeout)
|
|
mod_timer(&uart->timer, jiffies + uart->timeout);
|
|
else
|
|
/* A zero value means disable timeout feature */
|
|
omap_uart_block_sleep(uart);
|
|
|
|
return n;
|
|
}
|
|
|
|
static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
|
|
sleep_timeout_store);
|
|
#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
|
|
#else
|
|
static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
|
|
static void omap_uart_block_sleep(struct omap_uart_state *uart)
|
|
{
|
|
/* Needed to enable UART clocks when built without CONFIG_PM */
|
|
omap_uart_enable_clocks(uart);
|
|
}
|
|
#define DEV_CREATE_FILE(dev, attr)
|
|
#endif /* CONFIG_PM */
|
|
|
|
#ifndef CONFIG_SERIAL_OMAP
|
|
/*
|
|
* Override the default 8250 read handler: mem_serial_in()
|
|
* Empty RX fifo read causes an abort on omap3630 and omap4
|
|
* This function makes sure that an empty rx fifo is not read on these silicons
|
|
* (OMAP1/2/3430 are not affected)
|
|
*/
|
|
static unsigned int serial_in_override(struct uart_port *up, int offset)
|
|
{
|
|
if (UART_RX == offset) {
|
|
unsigned int lsr;
|
|
lsr = __serial_read_reg(up, UART_LSR);
|
|
if (!(lsr & UART_LSR_DR))
|
|
return -EPERM;
|
|
}
|
|
|
|
return __serial_read_reg(up, offset);
|
|
}
|
|
|
|
static void serial_out_override(struct uart_port *up, int offset, int value)
|
|
{
|
|
unsigned int status, tmout = 10000;
|
|
|
|
status = __serial_read_reg(up, UART_LSR);
|
|
while (!(status & UART_LSR_THRE)) {
|
|
/* Wait up to 10ms for the character(s) to be sent. */
|
|
if (--tmout == 0)
|
|
break;
|
|
udelay(1);
|
|
status = __serial_read_reg(up, UART_LSR);
|
|
}
|
|
__serial_write_reg(up, offset, value);
|
|
}
|
|
#endif
|
|
|
|
static int __init omap_serial_early_init(void)
|
|
{
|
|
int i = 0;
|
|
|
|
do {
|
|
char oh_name[MAX_UART_HWMOD_NAME_LEN];
|
|
struct omap_hwmod *oh;
|
|
struct omap_uart_state *uart;
|
|
|
|
snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
|
|
"uart%d", i + 1);
|
|
oh = omap_hwmod_lookup(oh_name);
|
|
if (!oh)
|
|
break;
|
|
|
|
uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
|
|
if (WARN_ON(!uart))
|
|
return -ENODEV;
|
|
|
|
uart->oh = oh;
|
|
uart->num = i++;
|
|
list_add_tail(&uart->node, &uart_list);
|
|
num_uarts++;
|
|
|
|
/*
|
|
* NOTE: omap_hwmod_setup*() has not yet been called,
|
|
* so no hwmod functions will work yet.
|
|
*/
|
|
|
|
/*
|
|
* During UART early init, device need to be probed
|
|
* to determine SoC specific init before omap_device
|
|
* is ready. Therefore, don't allow idle here
|
|
*/
|
|
uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
|
|
} while (1);
|
|
|
|
return 0;
|
|
}
|
|
core_initcall(omap_serial_early_init);
|
|
|
|
/**
|
|
* omap_serial_init_port() - initialize single serial port
|
|
* @bdata: port specific board data pointer
|
|
*
|
|
* This function initialies serial driver for given port only.
|
|
* Platforms can call this function instead of omap_serial_init()
|
|
* if they don't plan to use all available UARTs as serial ports.
|
|
*
|
|
* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
|
|
* use only one of the two.
|
|
*/
|
|
void __init omap_serial_init_port(struct omap_board_data *bdata)
|
|
{
|
|
struct omap_uart_state *uart;
|
|
struct omap_hwmod *oh;
|
|
struct omap_device *od;
|
|
void *pdata = NULL;
|
|
u32 pdata_size = 0;
|
|
char *name;
|
|
#ifndef CONFIG_SERIAL_OMAP
|
|
struct plat_serial8250_port ports[2] = {
|
|
{},
|
|
{.flags = 0},
|
|
};
|
|
struct plat_serial8250_port *p = &ports[0];
|
|
#else
|
|
struct omap_uart_port_info omap_up;
|
|
#endif
|
|
|
|
if (WARN_ON(!bdata))
|
|
return;
|
|
if (WARN_ON(bdata->id < 0))
|
|
return;
|
|
if (WARN_ON(bdata->id >= num_uarts))
|
|
return;
|
|
|
|
list_for_each_entry(uart, &uart_list, node)
|
|
if (bdata->id == uart->num)
|
|
break;
|
|
|
|
oh = uart->oh;
|
|
uart->dma_enabled = 0;
|
|
#ifndef CONFIG_SERIAL_OMAP
|
|
name = "serial8250";
|
|
|
|
/*
|
|
* !! 8250 driver does not use standard IORESOURCE* It
|
|
* has it's own custom pdata that can be taken from
|
|
* the hwmod resource data. But, this needs to be
|
|
* done after the build.
|
|
*
|
|
* ?? does it have to be done before the register ??
|
|
* YES, because platform_device_data_add() copies
|
|
* pdata, it does not use a pointer.
|
|
*/
|
|
p->flags = UPF_BOOT_AUTOCONF;
|
|
p->iotype = UPIO_MEM;
|
|
p->regshift = 2;
|
|
p->uartclk = OMAP24XX_BASE_BAUD * 16;
|
|
p->irq = oh->mpu_irqs[0].irq;
|
|
p->mapbase = oh->slaves[0]->addr->pa_start;
|
|
p->membase = omap_hwmod_get_mpu_rt_va(oh);
|
|
p->irqflags = IRQF_SHARED;
|
|
p->private_data = uart;
|
|
|
|
/*
|
|
* omap44xx, ti816x: Never read empty UART fifo
|
|
* omap3xxx: Never read empty UART fifo on UARTs
|
|
* with IP rev >=0x52
|
|
*/
|
|
uart->regshift = p->regshift;
|
|
uart->membase = p->membase;
|
|
if (cpu_is_omap44xx() || cpu_is_ti816x())
|
|
uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
|
|
else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
|
|
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
|
|
uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
|
|
|
|
if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
|
|
p->serial_in = serial_in_override;
|
|
p->serial_out = serial_out_override;
|
|
}
|
|
|
|
pdata = &ports[0];
|
|
pdata_size = 2 * sizeof(struct plat_serial8250_port);
|
|
#else
|
|
|
|
name = DRIVER_NAME;
|
|
|
|
omap_up.dma_enabled = uart->dma_enabled;
|
|
omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
|
|
omap_up.mapbase = oh->slaves[0]->addr->pa_start;
|
|
omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
|
|
omap_up.irqflags = IRQF_SHARED;
|
|
omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
|
|
|
|
pdata = &omap_up;
|
|
pdata_size = sizeof(struct omap_uart_port_info);
|
|
#endif
|
|
|
|
if (WARN_ON(!oh))
|
|
return;
|
|
|
|
od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
|
|
omap_uart_latency,
|
|
ARRAY_SIZE(omap_uart_latency), false);
|
|
WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
|
|
name, oh->name);
|
|
|
|
oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
|
|
|
|
uart->irq = oh->mpu_irqs[0].irq;
|
|
uart->regshift = 2;
|
|
uart->mapbase = oh->slaves[0]->addr->pa_start;
|
|
uart->membase = omap_hwmod_get_mpu_rt_va(oh);
|
|
uart->pdev = &od->pdev;
|
|
|
|
oh->dev_attr = uart;
|
|
|
|
console_lock(); /* in case the earlycon is on the UART */
|
|
|
|
/*
|
|
* Because of early UART probing, UART did not get idled
|
|
* on init. Now that omap_device is ready, ensure full idle
|
|
* before doing omap_device_enable().
|
|
*/
|
|
omap_hwmod_idle(uart->oh);
|
|
|
|
omap_device_enable(uart->pdev);
|
|
omap_uart_idle_init(uart);
|
|
omap_uart_reset(uart);
|
|
omap_hwmod_enable_wakeup(uart->oh);
|
|
omap_device_idle(uart->pdev);
|
|
|
|
/*
|
|
* Need to block sleep long enough for interrupt driven
|
|
* driver to start. Console driver is in polling mode
|
|
* so device needs to be kept enabled while polling driver
|
|
* is in use.
|
|
*/
|
|
if (uart->timeout)
|
|
uart->timeout = (30 * HZ);
|
|
omap_uart_block_sleep(uart);
|
|
uart->timeout = DEFAULT_TIMEOUT;
|
|
|
|
console_unlock();
|
|
|
|
if ((cpu_is_omap34xx() && uart->padconf) ||
|
|
(uart->wk_en && uart->wk_mask)) {
|
|
device_init_wakeup(&od->pdev.dev, true);
|
|
DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
|
|
}
|
|
|
|
/* Enable the MDR1 errata for OMAP3 */
|
|
if (cpu_is_omap34xx() && !cpu_is_ti816x())
|
|
uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
|
|
}
|
|
|
|
/**
|
|
* omap_serial_init() - initialize all supported serial ports
|
|
*
|
|
* Initializes all available UARTs as serial ports. Platforms
|
|
* can call this function when they want to have default behaviour
|
|
* for serial ports (e.g initialize them all as serial ports).
|
|
*/
|
|
void __init omap_serial_init(void)
|
|
{
|
|
struct omap_uart_state *uart;
|
|
struct omap_board_data bdata;
|
|
|
|
list_for_each_entry(uart, &uart_list, node) {
|
|
bdata.id = uart->num;
|
|
bdata.flags = 0;
|
|
bdata.pads = NULL;
|
|
bdata.pads_cnt = 0;
|
|
omap_serial_init_port(&bdata);
|
|
|
|
}
|
|
}
|