mirror of https://gitee.com/openkylin/linux.git
208 lines
5.3 KiB
C
208 lines
5.3 KiB
C
/*
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* OMAP 32ksynctimer/counter_32k-related code
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*
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* Copyright (C) 2009 Texas Instruments
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* Copyright (C) 2010 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <asm/sched_clock.h>
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#include <plat/common.h>
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#include <plat/board.h>
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#include <plat/clock.h>
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/*
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* 32KHz clocksource ... always available, on pretty most chips except
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* OMAP 730 and 1510. Other timers could be used as clocksources, with
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* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
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* but systems won't necessarily want to spend resources that way.
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*/
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#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
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#include <linux/clocksource.h>
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/*
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* offset_32k holds the init time counter value. It is then subtracted
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* from every counter read to achieve a counter that counts time from the
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* kernel boot (needed for sched_clock()).
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*/
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static u32 offset_32k __read_mostly;
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#ifdef CONFIG_ARCH_OMAP16XX
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static cycle_t notrace omap16xx_32k_read(struct clocksource *cs)
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{
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return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
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}
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#else
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#define omap16xx_32k_read NULL
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#endif
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#ifdef CONFIG_SOC_OMAP2420
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static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
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{
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return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
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}
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#else
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#define omap2420_32k_read NULL
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#endif
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#ifdef CONFIG_SOC_OMAP2430
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static cycle_t notrace omap2430_32k_read(struct clocksource *cs)
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{
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return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
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}
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#else
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#define omap2430_32k_read NULL
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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static cycle_t notrace omap34xx_32k_read(struct clocksource *cs)
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{
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return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
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}
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#else
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#define omap34xx_32k_read NULL
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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static cycle_t notrace omap44xx_32k_read(struct clocksource *cs)
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{
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return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
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}
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#else
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#define omap44xx_32k_read NULL
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#endif
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/*
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* Kernel assumes that sched_clock can be called early but may not have
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* things ready yet.
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*/
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static cycle_t notrace omap_32k_read_dummy(struct clocksource *cs)
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{
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return 0;
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}
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static struct clocksource clocksource_32k = {
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.name = "32k_counter",
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.rating = 250,
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.read = omap_32k_read_dummy,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* Returns current time from boot in nsecs. It's OK for this to wrap
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* around for now, as it's just a relative time stamp.
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*/
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static DEFINE_CLOCK_DATA(cd);
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/*
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* Constants generated by clocks_calc_mult_shift(m, s, 32768, NSEC_PER_SEC, 60).
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* This gives a resolution of about 30us and a wrap period of about 36hrs.
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*/
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#define SC_MULT 4000000000u
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#define SC_SHIFT 17
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static inline unsigned long long notrace _omap_32k_sched_clock(void)
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{
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u32 cyc = clocksource_32k.read(&clocksource_32k);
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return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
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}
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#ifndef CONFIG_OMAP_MPU_TIMER
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unsigned long long notrace sched_clock(void)
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{
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return _omap_32k_sched_clock();
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}
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#else
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unsigned long long notrace omap_32k_sched_clock(void)
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{
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return _omap_32k_sched_clock();
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}
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#endif
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static void notrace omap_update_sched_clock(void)
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{
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u32 cyc = clocksource_32k.read(&clocksource_32k);
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update_sched_clock(&cd, cyc, (u32)~0);
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}
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/**
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* read_persistent_clock - Return time from a persistent clock.
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*
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* Reads the time from a source which isn't disabled during PM, the
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* 32k sync timer. Convert the cycles elapsed since last read into
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* nsecs and adds to a monotonically increasing timespec.
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*/
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static struct timespec persistent_ts;
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static cycles_t cycles, last_cycles;
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void read_persistent_clock(struct timespec *ts)
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{
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unsigned long long nsecs;
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cycles_t delta;
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struct timespec *tsp = &persistent_ts;
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last_cycles = cycles;
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cycles = clocksource_32k.read(&clocksource_32k);
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delta = cycles - last_cycles;
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nsecs = clocksource_cyc2ns(delta,
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clocksource_32k.mult, clocksource_32k.shift);
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timespec_add_ns(tsp, nsecs);
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*ts = *tsp;
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}
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int __init omap_init_clocksource_32k(void)
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{
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static char err[] __initdata = KERN_ERR
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"%s: can't register clocksource!\n";
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if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
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struct clk *sync_32k_ick;
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if (cpu_is_omap16xx())
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clocksource_32k.read = omap16xx_32k_read;
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else if (cpu_is_omap2420())
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clocksource_32k.read = omap2420_32k_read;
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else if (cpu_is_omap2430())
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clocksource_32k.read = omap2430_32k_read;
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else if (cpu_is_omap34xx())
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clocksource_32k.read = omap34xx_32k_read;
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else if (cpu_is_omap44xx())
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clocksource_32k.read = omap44xx_32k_read;
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else
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return -ENODEV;
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sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
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if (!IS_ERR(sync_32k_ick))
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clk_enable(sync_32k_ick);
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offset_32k = clocksource_32k.read(&clocksource_32k);
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if (clocksource_register_hz(&clocksource_32k, 32768))
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printk(err, clocksource_32k.name);
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init_fixed_sched_clock(&cd, omap_update_sched_clock, 32,
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32768, SC_MULT, SC_SHIFT);
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}
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return 0;
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}
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