mirror of https://gitee.com/openkylin/linux.git
207 lines
5.4 KiB
C
207 lines
5.4 KiB
C
/* arch/arm/plat-samsung/gpiolib.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* SAMSUNG - GPIOlib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <plat/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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#ifndef DEBUG_GPIO
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#define gpio_dbg(x...) do { } while (0)
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#else
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#define gpio_dbg(x...) printk(KERN_DEBUG x)
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#endif
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/* The samsung_gpiolib_4bit routines are to control the gpio banks where
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* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
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* following example:
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*
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* base + 0x00: Control register, 4 bits per gpio
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x04: Data register, 1 bit per gpio
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* bit n: data bit n
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*
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* Note, since the data register is one bit per gpio and is at base + 0x4
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* we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
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* the output.
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*/
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static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long con;
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con = __raw_readl(base + GPIOCON_OFF);
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con &= ~(0xf << con_4bit_shift(offset));
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__raw_writel(con, base + GPIOCON_OFF);
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gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
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return 0;
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}
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static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long con;
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unsigned long dat;
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con = __raw_readl(base + GPIOCON_OFF);
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con &= ~(0xf << con_4bit_shift(offset));
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con |= 0x1 << con_4bit_shift(offset);
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dat = __raw_readl(base + GPIODAT_OFF);
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if (value)
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dat |= 1 << offset;
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else
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dat &= ~(1 << offset);
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__raw_writel(dat, base + GPIODAT_OFF);
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__raw_writel(con, base + GPIOCON_OFF);
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__raw_writel(dat, base + GPIODAT_OFF);
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gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
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return 0;
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}
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/* The next set of routines are for the case where the GPIO configuration
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* registers are 4 bits per GPIO but there is more than one register (the
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* bank has more than 8 GPIOs.
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*
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* This case is the similar to the 4 bit case, but the registers are as
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* follows:
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*
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* base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x08: Data register, 1 bit per gpio
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* bit n: data bit n
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*
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* To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
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* store the 'base + 0x4' address so that these routines see the data
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* register at ourchip->base + 0x04.
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*/
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static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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void __iomem *regcon = base;
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unsigned long con;
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if (offset > 7)
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offset -= 8;
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else
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regcon -= 4;
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con = __raw_readl(regcon);
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con &= ~(0xf << con_4bit_shift(offset));
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__raw_writel(con, regcon);
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gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
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return 0;
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}
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static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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void __iomem *regcon = base;
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unsigned long con;
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unsigned long dat;
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unsigned con_offset = offset;
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if (con_offset > 7)
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con_offset -= 8;
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else
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regcon -= 4;
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con = __raw_readl(regcon);
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con &= ~(0xf << con_4bit_shift(con_offset));
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con |= 0x1 << con_4bit_shift(con_offset);
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dat = __raw_readl(base + GPIODAT_OFF);
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if (value)
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dat |= 1 << offset;
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else
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dat &= ~(1 << offset);
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__raw_writel(dat, base + GPIODAT_OFF);
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__raw_writel(con, regcon);
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__raw_writel(dat, base + GPIODAT_OFF);
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gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
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return 0;
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}
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void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
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{
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chip->chip.direction_input = samsung_gpiolib_4bit_input;
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chip->chip.direction_output = samsung_gpiolib_4bit_output;
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chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
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}
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void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
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{
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chip->chip.direction_input = samsung_gpiolib_4bit2_input;
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chip->chip.direction_output = samsung_gpiolib_4bit2_output;
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chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
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}
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void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
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int nr_chips)
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{
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for (; nr_chips > 0; nr_chips--, chip++) {
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samsung_gpiolib_add_4bit(chip);
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s3c_gpiolib_add(chip);
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}
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}
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void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
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int nr_chips)
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{
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for (; nr_chips > 0; nr_chips--, chip++) {
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samsung_gpiolib_add_4bit2(chip);
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s3c_gpiolib_add(chip);
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}
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}
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void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
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int nr_chips)
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{
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for (; nr_chips > 0; nr_chips--, chip++)
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s3c_gpiolib_add(chip);
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}
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