mirror of https://gitee.com/openkylin/linux.git
286 lines
6.5 KiB
C
286 lines
6.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009-2012 Cavium, Inc.
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*/
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#include <linux/platform_device.h>
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#include <linux/of_mdio.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/gfp.h>
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#include <linux/phy.h>
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#include <linux/io.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-smix-defs.h>
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#define DRV_VERSION "1.0"
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#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"
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#define SMI_CMD 0x0
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#define SMI_WR_DAT 0x8
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#define SMI_RD_DAT 0x10
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#define SMI_CLK 0x18
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#define SMI_EN 0x20
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enum octeon_mdiobus_mode {
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UNINIT = 0,
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C22,
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C45
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};
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struct octeon_mdiobus {
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struct mii_bus *mii_bus;
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u64 register_base;
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resource_size_t mdio_phys;
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resource_size_t regsize;
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enum octeon_mdiobus_mode mode;
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int phy_irq[PHY_MAX_ADDR];
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};
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static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
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enum octeon_mdiobus_mode m)
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{
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union cvmx_smix_clk smi_clk;
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if (m == p->mode)
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return;
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smi_clk.u64 = cvmx_read_csr(p->register_base + SMI_CLK);
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smi_clk.s.mode = (m == C45) ? 1 : 0;
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smi_clk.s.preamble = 1;
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cvmx_write_csr(p->register_base + SMI_CLK, smi_clk.u64);
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p->mode = m;
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}
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static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
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int phy_id, int regnum)
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{
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_wr_dat smi_wr;
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int timeout = 1000;
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octeon_mdiobus_set_mode(p, C45);
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smi_wr.u64 = 0;
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smi_wr.s.dat = regnum & 0xffff;
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cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
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regnum = (regnum >> 16) & 0x1f;
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
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} while (smi_wr.s.pending && --timeout);
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if (timeout <= 0)
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return -EIO;
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return 0;
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}
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static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
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{
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struct octeon_mdiobus *p = bus->priv;
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_rd_dat smi_rd;
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unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
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int timeout = 1000;
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if (regnum & MII_ADDR_C45) {
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int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
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if (r < 0)
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return r;
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regnum = (regnum >> 16) & 0x1f;
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op = 3; /* MDIO_CLAUSE_45_READ */
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} else {
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octeon_mdiobus_set_mode(p, C22);
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}
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = op;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT);
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} while (smi_rd.s.pending && --timeout);
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if (smi_rd.s.val)
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return smi_rd.s.dat;
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else
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return -EIO;
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}
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static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
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int regnum, u16 val)
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{
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struct octeon_mdiobus *p = bus->priv;
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_wr_dat smi_wr;
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unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
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int timeout = 1000;
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if (regnum & MII_ADDR_C45) {
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int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
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if (r < 0)
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return r;
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regnum = (regnum >> 16) & 0x1f;
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op = 1; /* MDIO_CLAUSE_45_WRITE */
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} else {
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octeon_mdiobus_set_mode(p, C22);
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}
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smi_wr.u64 = 0;
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smi_wr.s.dat = val;
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cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = op;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
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} while (smi_wr.s.pending && --timeout);
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if (timeout <= 0)
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return -EIO;
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return 0;
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}
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static int octeon_mdiobus_probe(struct platform_device *pdev)
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{
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struct octeon_mdiobus *bus;
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struct resource *res_mem;
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union cvmx_smix_en smi_en;
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int err = -ENOENT;
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bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
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if (!bus)
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return -ENOMEM;
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res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res_mem == NULL) {
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dev_err(&pdev->dev, "found no memory resource\n");
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err = -ENXIO;
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goto fail;
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}
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bus->mdio_phys = res_mem->start;
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bus->regsize = resource_size(res_mem);
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if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize,
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res_mem->name)) {
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dev_err(&pdev->dev, "request_mem_region failed\n");
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goto fail;
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}
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bus->register_base =
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(u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize);
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bus->mii_bus = mdiobus_alloc();
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if (!bus->mii_bus)
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goto fail;
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smi_en.u64 = 0;
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smi_en.s.en = 1;
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cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
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bus->mii_bus->priv = bus;
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bus->mii_bus->irq = bus->phy_irq;
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bus->mii_bus->name = "mdio-octeon";
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snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
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bus->mii_bus->parent = &pdev->dev;
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bus->mii_bus->read = octeon_mdiobus_read;
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bus->mii_bus->write = octeon_mdiobus_write;
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dev_set_drvdata(&pdev->dev, bus);
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err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node);
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if (err)
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goto fail_register;
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dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
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return 0;
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fail_register:
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mdiobus_free(bus->mii_bus);
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fail:
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smi_en.u64 = 0;
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cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
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return err;
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}
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static int octeon_mdiobus_remove(struct platform_device *pdev)
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{
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struct octeon_mdiobus *bus;
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union cvmx_smix_en smi_en;
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bus = dev_get_drvdata(&pdev->dev);
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mdiobus_unregister(bus->mii_bus);
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mdiobus_free(bus->mii_bus);
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smi_en.u64 = 0;
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cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
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return 0;
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}
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static struct of_device_id octeon_mdiobus_match[] = {
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{
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.compatible = "cavium,octeon-3860-mdio",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_mdiobus_match);
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static struct platform_driver octeon_mdiobus_driver = {
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.driver = {
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.name = "mdio-octeon",
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.owner = THIS_MODULE,
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.of_match_table = octeon_mdiobus_match,
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},
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.probe = octeon_mdiobus_probe,
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.remove = octeon_mdiobus_remove,
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};
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void octeon_mdiobus_force_mod_depencency(void)
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{
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/* Let ethernet drivers force us to be loaded. */
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}
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EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);
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module_platform_driver(octeon_mdiobus_driver);
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MODULE_DESCRIPTION(DRV_DESCRIPTION);
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MODULE_VERSION(DRV_VERSION);
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MODULE_AUTHOR("David Daney");
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MODULE_LICENSE("GPL");
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