mirror of https://gitee.com/openkylin/linux.git
509 lines
14 KiB
C
509 lines
14 KiB
C
/*
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* SH-X3 Prototype Setup
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*
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* Copyright (C) 2007 - 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/sh_timer.h>
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#include <cpu/shx3.h>
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#include <asm/mmzone.h>
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/*
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* This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
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* INTEVT values overlap with the FPU EXPEVT ones, requiring special
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* demuxing in the exception dispatch path.
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*
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* As this overlap is something that never should have made it in to
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* silicon in the first place, we just refuse to deal with the port at
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* all rather than adding infrastructure to hack around it.
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*/
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xffc30000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCIF,
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.irqs = { 40, 41, 43, 42 },
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct plat_sci_port scif1_platform_data = {
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.mapbase = 0xffc40000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCIF,
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.irqs = { 44, 45, 47, 46 },
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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static struct plat_sci_port scif2_platform_data = {
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.mapbase = 0xffc60000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCIF,
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.irqs = { 52, 53, 55, 54 },
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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static struct sh_timer_config tmu0_platform_data = {
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.channel_offset = 0x04,
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.timer_bit = 0,
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.clockevent_rating = 200,
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};
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static struct resource tmu0_resources[] = {
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[0] = {
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.start = 0xffc10008,
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.end = 0xffc10013,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 16,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu0_device = {
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.name = "sh_tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu0_platform_data,
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},
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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};
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static struct sh_timer_config tmu1_platform_data = {
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clocksource_rating = 200,
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};
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static struct resource tmu1_resources[] = {
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[0] = {
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.start = 0xffc10014,
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.end = 0xffc1001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 17,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu1_device = {
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.name = "sh_tmu",
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.id = 1,
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.dev = {
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.platform_data = &tmu1_platform_data,
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},
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.resource = tmu1_resources,
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.num_resources = ARRAY_SIZE(tmu1_resources),
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};
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static struct sh_timer_config tmu2_platform_data = {
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.channel_offset = 0x1c,
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.timer_bit = 2,
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};
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static struct resource tmu2_resources[] = {
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[0] = {
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.start = 0xffc10020,
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.end = 0xffc1002f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 18,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu2_device = {
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.name = "sh_tmu",
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.id = 2,
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.dev = {
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.platform_data = &tmu2_platform_data,
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},
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.resource = tmu2_resources,
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.num_resources = ARRAY_SIZE(tmu2_resources),
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};
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static struct sh_timer_config tmu3_platform_data = {
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.channel_offset = 0x04,
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.timer_bit = 0,
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};
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static struct resource tmu3_resources[] = {
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[0] = {
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.start = 0xffc20008,
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.end = 0xffc20013,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 19,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu3_device = {
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.name = "sh_tmu",
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.id = 3,
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.dev = {
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.platform_data = &tmu3_platform_data,
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},
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.resource = tmu3_resources,
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.num_resources = ARRAY_SIZE(tmu3_resources),
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};
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static struct sh_timer_config tmu4_platform_data = {
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.channel_offset = 0x10,
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.timer_bit = 1,
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};
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static struct resource tmu4_resources[] = {
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[0] = {
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.start = 0xffc20014,
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.end = 0xffc2001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 20,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu4_device = {
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.name = "sh_tmu",
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.id = 4,
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.dev = {
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.platform_data = &tmu4_platform_data,
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},
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.resource = tmu4_resources,
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.num_resources = ARRAY_SIZE(tmu4_resources),
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};
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static struct sh_timer_config tmu5_platform_data = {
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.channel_offset = 0x1c,
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.timer_bit = 2,
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};
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static struct resource tmu5_resources[] = {
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[0] = {
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.start = 0xffc20020,
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.end = 0xffc2002b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 21,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu5_device = {
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.name = "sh_tmu",
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.id = 5,
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.dev = {
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.platform_data = &tmu5_platform_data,
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},
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.resource = tmu5_resources,
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.num_resources = ARRAY_SIZE(tmu5_resources),
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};
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static struct platform_device *shx3_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&tmu0_device,
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&tmu1_device,
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&tmu2_device,
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&tmu3_device,
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&tmu4_device,
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&tmu5_device,
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};
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static int __init shx3_devices_setup(void)
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{
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return platform_add_devices(shx3_early_devices,
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ARRAY_SIZE(shx3_early_devices));
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}
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arch_initcall(shx3_devices_setup);
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void __init plat_early_device_setup(void)
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{
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early_platform_add_devices(shx3_early_devices,
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ARRAY_SIZE(shx3_early_devices));
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}
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
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IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
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IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
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IRL_HHLL, IRL_HHLH, IRL_HHHL,
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IRQ0, IRQ1, IRQ2, IRQ3,
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HUDII,
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TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
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PCII0, PCII1, PCII2, PCII3, PCII4,
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PCII5, PCII6, PCII7, PCII8, PCII9,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
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SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI,
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DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
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DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
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DU,
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DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
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DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
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IIC, VIN0, VIN1, VCORE0, ATAPI,
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DTU0, DTU1, DTU2, DTU3,
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FE0, FE1,
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GPIO0, GPIO1, GPIO2, GPIO3,
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PAM, IRM,
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INTICI0, INTICI1, INTICI2, INTICI3,
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INTICI4, INTICI5, INTICI6, INTICI7,
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/* interrupt groups */
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IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
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DMAC0, DMAC1,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(HUDII, 0x3e0),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
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INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0),
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INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520),
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INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560),
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INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0),
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INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0),
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INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620),
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INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
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INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
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INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
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INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
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INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
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INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
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INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
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INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960),
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INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0),
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INTC_VECT(DMAC0_DMAE, 0x9c0),
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INTC_VECT(DU, 0x9e0),
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INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20),
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INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60),
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INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0),
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INTC_VECT(DMAC1_DMAE, 0xac0),
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INTC_VECT(IIC, 0xae0),
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INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
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INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
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INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20),
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INTC_VECT(DTU0, 0xc40),
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INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80),
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INTC_VECT(DTU1, 0xca0),
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INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0),
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INTC_VECT(DTU2, 0xd00),
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INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40),
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INTC_VECT(DTU3, 0xd60),
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INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
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INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
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INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
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INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
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INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
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INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
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INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
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INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
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IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
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IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
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IRL_HHLL, IRL_HHLH, IRL_HHHL),
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INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
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INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
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INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
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DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
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INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
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DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
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};
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#define INT2DISTCR0 0xfe4108a0
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#define INT2DISTCR1 0xfe4108a4
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#define INT2DISTCR2 0xfe4108a8
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
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{ IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
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{ IRL } },
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{ 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */
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{ FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
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DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
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0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
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INTC_SMP_BALANCING(INT2DISTCR0) },
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{ 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
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{ 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
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PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
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PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
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DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
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DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
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DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 },
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INTC_SMP_BALANCING(INT2DISTCR1) },
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{ 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
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SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
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SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
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SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI },
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INTC_SMP_BALANCING(INT2DISTCR2) },
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
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TMU3, TMU2, TMU1, TMU0 } },
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{ 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
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SCIF3, SCIF2,
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SCIF1, SCIF0 } },
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{ 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
|
|
PCII56789, PCII4,
|
|
PCII3, PCII2,
|
|
PCII1, PCII0 } },
|
|
{ 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
|
|
VIN1, VIN0, IIC, DU} },
|
|
{ 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
|
|
GPIO2, GPIO1, GPIO0, IRM } },
|
|
{ 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
|
|
{ INTICI7, INTICI6, INTICI5, INTICI4,
|
|
INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 4) },
|
|
};
|
|
|
|
static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups,
|
|
mask_registers, prio_registers, NULL);
|
|
|
|
/* Support for external interrupt pins in IRQ mode */
|
|
static struct intc_vect vectors_irq[] __initdata = {
|
|
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
|
|
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
|
|
};
|
|
|
|
static struct intc_sense_reg sense_registers[] __initdata = {
|
|
{ 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
|
};
|
|
|
|
static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
|
|
mask_registers, prio_registers, sense_registers);
|
|
|
|
/* External interrupt pins in IRL mode */
|
|
static struct intc_vect vectors_irl[] __initdata = {
|
|
INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
|
|
INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
|
|
INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
|
|
INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
|
|
INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
|
|
INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
|
|
INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
|
|
INTC_VECT(IRL_HHHL, 0x3c0),
|
|
};
|
|
|
|
static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
|
|
mask_registers, prio_registers, NULL);
|
|
|
|
void __init plat_irq_setup_pins(int mode)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (mode) {
|
|
case IRQ_MODE_IRQ:
|
|
ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name);
|
|
ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name);
|
|
ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name);
|
|
ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name);
|
|
|
|
if (unlikely(ret)) {
|
|
pr_err("Failed to set IRQ mode\n");
|
|
return;
|
|
}
|
|
|
|
register_intc_controller(&intc_desc_irq);
|
|
break;
|
|
case IRQ_MODE_IRL3210:
|
|
ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name);
|
|
ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name);
|
|
ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name);
|
|
ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name);
|
|
|
|
if (unlikely(ret)) {
|
|
pr_err("Failed to set IRL mode\n");
|
|
return;
|
|
}
|
|
|
|
register_intc_controller(&intc_desc_irl);
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
void __init plat_irq_setup(void)
|
|
{
|
|
reserve_intc_vectors(vectors_irq, ARRAY_SIZE(vectors_irq));
|
|
reserve_intc_vectors(vectors_irl, ARRAY_SIZE(vectors_irl));
|
|
|
|
register_intc_controller(&intc_desc);
|
|
}
|
|
|
|
void __init plat_mem_setup(void)
|
|
{
|
|
unsigned int nid = 1;
|
|
|
|
/* Register CPU#0 URAM space as Node 1 */
|
|
setup_bootmem_node(nid++, 0x145f0000, 0x14610000); /* CPU0 */
|
|
|
|
#if 0
|
|
/* XXX: Not yet.. */
|
|
setup_bootmem_node(nid++, 0x14df0000, 0x14e10000); /* CPU1 */
|
|
setup_bootmem_node(nid++, 0x155f0000, 0x15610000); /* CPU2 */
|
|
setup_bootmem_node(nid++, 0x15df0000, 0x15e10000); /* CPU3 */
|
|
#endif
|
|
|
|
setup_bootmem_node(nid++, 0x16000000, 0x16020000); /* CSM */
|
|
}
|