mirror of https://gitee.com/openkylin/linux.git
418 lines
10 KiB
C
418 lines
10 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_vm.h"
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#define BAR1_VM_BASE 0x0020000000ULL
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#define BAR1_VM_SIZE pci_resource_len(dev->pdev, 1)
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#define BAR3_VM_BASE 0x0000000000ULL
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#define BAR3_VM_SIZE pci_resource_len(dev->pdev, 3)
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struct nv50_instmem_priv {
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uint32_t save1700[5]; /* 0x1700->0x1710 */
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struct nouveau_gpuobj *bar1_dmaobj;
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struct nouveau_gpuobj *bar3_dmaobj;
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};
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static void
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nv50_channel_del(struct nouveau_channel **pchan)
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{
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struct nouveau_channel *chan;
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chan = *pchan;
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*pchan = NULL;
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if (!chan)
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return;
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nouveau_gpuobj_ref(NULL, &chan->ramfc);
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nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);
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nouveau_gpuobj_ref(NULL, &chan->vm_pd);
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if (chan->ramin_heap.free_stack.next)
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drm_mm_takedown(&chan->ramin_heap);
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nouveau_gpuobj_ref(NULL, &chan->ramin);
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kfree(chan);
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}
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static int
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nv50_channel_new(struct drm_device *dev, u32 size, struct nouveau_vm *vm,
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struct nouveau_channel **pchan)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 pgd = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200;
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u32 fc = (dev_priv->chipset == 0x50) ? 0x0000 : 0x4200;
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struct nouveau_channel *chan;
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int ret, i;
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chan = kzalloc(sizeof(*chan), GFP_KERNEL);
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if (!chan)
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return -ENOMEM;
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chan->dev = dev;
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ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
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if (ret) {
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nv50_channel_del(&chan);
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return ret;
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}
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ret = drm_mm_init(&chan->ramin_heap, 0x6000, chan->ramin->size);
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if (ret) {
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nv50_channel_del(&chan);
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return ret;
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}
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ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst == ~0 ? ~0 :
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chan->ramin->pinst + pgd,
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chan->ramin->vinst + pgd,
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0x4000, NVOBJ_FLAG_ZERO_ALLOC,
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&chan->vm_pd);
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if (ret) {
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nv50_channel_del(&chan);
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return ret;
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}
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for (i = 0; i < 0x4000; i += 8) {
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nv_wo32(chan->vm_pd, i + 0, 0x00000000);
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nv_wo32(chan->vm_pd, i + 4, 0xdeadcafe);
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}
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ret = nouveau_vm_ref(vm, &chan->vm, chan->vm_pd);
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if (ret) {
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nv50_channel_del(&chan);
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return ret;
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}
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ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst == ~0 ? ~0 :
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chan->ramin->pinst + fc,
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chan->ramin->vinst + fc, 0x100,
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NVOBJ_FLAG_ZERO_ALLOC, &chan->ramfc);
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if (ret) {
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nv50_channel_del(&chan);
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return ret;
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}
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*pchan = chan;
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return 0;
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}
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int
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nv50_instmem_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_instmem_priv *priv;
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struct nouveau_channel *chan;
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struct nouveau_vm *vm;
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int ret, i;
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u32 tmp;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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dev_priv->engine.instmem.priv = priv;
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/* Save state, will restore at takedown. */
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for (i = 0x1700; i <= 0x1710; i += 4)
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priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
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/* Global PRAMIN heap */
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ret = drm_mm_init(&dev_priv->ramin_heap, 0, dev_priv->ramin_size);
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if (ret) {
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NV_ERROR(dev, "Failed to init RAMIN heap\n");
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goto error;
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}
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/* BAR3 */
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ret = nouveau_vm_new(dev, BAR3_VM_BASE, BAR3_VM_SIZE, BAR3_VM_BASE,
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29, 12, 16, &dev_priv->bar3_vm);
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if (ret)
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goto error;
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ret = nouveau_gpuobj_new(dev, NULL, (BAR3_VM_SIZE >> 12) * 8,
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0x1000, NVOBJ_FLAG_DONT_MAP |
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NVOBJ_FLAG_ZERO_ALLOC,
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&dev_priv->bar3_vm->pgt[0].obj);
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if (ret)
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goto error;
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dev_priv->bar3_vm->pgt[0].page_shift = 12;
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dev_priv->bar3_vm->pgt[0].refcount = 1;
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nv50_instmem_map(dev_priv->bar3_vm->pgt[0].obj);
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ret = nv50_channel_new(dev, 128 * 1024, dev_priv->bar3_vm, &chan);
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if (ret)
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goto error;
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dev_priv->channels.ptr[0] = dev_priv->channels.ptr[127] = chan;
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ret = nv50_gpuobj_dma_new(chan, 0x0000, BAR3_VM_BASE, BAR3_VM_SIZE,
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NV_MEM_TARGET_VM, NV_MEM_ACCESS_VM,
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NV_MEM_TYPE_VM, NV_MEM_COMP_VM,
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&priv->bar3_dmaobj);
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if (ret)
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goto error;
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nv_wr32(dev, 0x001704, 0x00000000 | (chan->ramin->vinst >> 12));
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nv_wr32(dev, 0x001704, 0x40000000 | (chan->ramin->vinst >> 12));
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nv_wr32(dev, 0x00170c, 0x80000000 | (priv->bar3_dmaobj->cinst >> 4));
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dev_priv->engine.instmem.flush(dev);
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dev_priv->ramin_available = true;
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tmp = nv_ro32(chan->ramin, 0);
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nv_wo32(chan->ramin, 0, ~tmp);
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if (nv_ro32(chan->ramin, 0) != ~tmp) {
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NV_ERROR(dev, "PRAMIN readback failed\n");
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ret = -EIO;
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goto error;
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}
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nv_wo32(chan->ramin, 0, tmp);
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/* BAR1 */
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ret = nouveau_vm_new(dev, BAR1_VM_BASE, BAR1_VM_SIZE, BAR1_VM_BASE,
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29, 12, 16, &vm);
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if (ret)
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goto error;
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ret = nouveau_vm_ref(vm, &dev_priv->bar1_vm, chan->vm_pd);
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if (ret)
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goto error;
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nouveau_vm_ref(NULL, &vm, NULL);
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ret = nv50_gpuobj_dma_new(chan, 0x0000, BAR1_VM_BASE, BAR1_VM_SIZE,
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NV_MEM_TARGET_VM, NV_MEM_ACCESS_VM,
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NV_MEM_TYPE_VM, NV_MEM_COMP_VM,
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&priv->bar1_dmaobj);
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if (ret)
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goto error;
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nv_wr32(dev, 0x001708, 0x80000000 | (priv->bar1_dmaobj->cinst >> 4));
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for (i = 0; i < 8; i++)
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nv_wr32(dev, 0x1900 + (i*4), 0);
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/* Create shared channel VM, space is reserved at the beginning
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* to catch "NULL pointer" references
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*/
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ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
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29, 12, 16, &dev_priv->chan_vm);
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if (ret)
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return ret;
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return 0;
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error:
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nv50_instmem_takedown(dev);
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return ret;
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}
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void
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nv50_instmem_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
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struct nouveau_channel *chan = dev_priv->channels.ptr[0];
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int i;
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NV_DEBUG(dev, "\n");
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if (!priv)
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return;
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dev_priv->ramin_available = false;
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nouveau_vm_ref(NULL, &dev_priv->chan_vm, NULL);
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for (i = 0x1700; i <= 0x1710; i += 4)
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nv_wr32(dev, i, priv->save1700[(i - 0x1700) / 4]);
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nouveau_gpuobj_ref(NULL, &priv->bar3_dmaobj);
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nouveau_gpuobj_ref(NULL, &priv->bar1_dmaobj);
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nouveau_vm_ref(NULL, &dev_priv->bar1_vm, chan->vm_pd);
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dev_priv->channels.ptr[127] = 0;
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nv50_channel_del(&dev_priv->channels.ptr[0]);
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nouveau_gpuobj_ref(NULL, &dev_priv->bar3_vm->pgt[0].obj);
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nouveau_vm_ref(NULL, &dev_priv->bar3_vm, NULL);
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if (dev_priv->ramin_heap.free_stack.next)
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drm_mm_takedown(&dev_priv->ramin_heap);
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dev_priv->engine.instmem.priv = NULL;
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kfree(priv);
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}
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int
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nv50_instmem_suspend(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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dev_priv->ramin_available = false;
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return 0;
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}
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void
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nv50_instmem_resume(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
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struct nouveau_channel *chan = dev_priv->channels.ptr[0];
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int i;
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/* Poke the relevant regs, and pray it works :) */
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nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12));
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nv_wr32(dev, NV50_PUNK_UNK1710, 0);
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nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12) |
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NV50_PUNK_BAR_CFG_BASE_VALID);
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nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->bar1_dmaobj->cinst >> 4) |
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NV50_PUNK_BAR1_CTXDMA_VALID);
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nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->bar3_dmaobj->cinst >> 4) |
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NV50_PUNK_BAR3_CTXDMA_VALID);
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for (i = 0; i < 8; i++)
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nv_wr32(dev, 0x1900 + (i*4), 0);
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dev_priv->ramin_available = true;
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}
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struct nv50_gpuobj_node {
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struct nouveau_vram *vram;
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struct nouveau_vma chan_vma;
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u32 align;
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};
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int
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nv50_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)
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{
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struct drm_device *dev = gpuobj->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
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struct nv50_gpuobj_node *node = NULL;
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int ret;
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node = kzalloc(sizeof(*node), GFP_KERNEL);
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if (!node)
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return -ENOMEM;
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node->align = align;
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size = (size + 4095) & ~4095;
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align = max(align, (u32)4096);
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ret = vram->get(dev, size, align, 0, 0, &node->vram);
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if (ret) {
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kfree(node);
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return ret;
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}
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gpuobj->vinst = node->vram->offset;
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if (gpuobj->flags & NVOBJ_FLAG_VM) {
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ret = nouveau_vm_get(dev_priv->chan_vm, size, 12,
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NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
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&node->chan_vma);
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if (ret) {
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vram->put(dev, &node->vram);
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kfree(node);
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return ret;
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}
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nouveau_vm_map(&node->chan_vma, node->vram);
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gpuobj->vinst = node->chan_vma.offset;
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}
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gpuobj->size = size;
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gpuobj->node = node;
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return 0;
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}
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void
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nv50_instmem_put(struct nouveau_gpuobj *gpuobj)
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{
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struct drm_device *dev = gpuobj->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
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struct nv50_gpuobj_node *node;
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node = gpuobj->node;
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gpuobj->node = NULL;
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if (node->chan_vma.node) {
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nouveau_vm_unmap(&node->chan_vma);
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nouveau_vm_put(&node->chan_vma);
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}
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vram->put(dev, &node->vram);
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kfree(node);
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}
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int
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nv50_instmem_map(struct nouveau_gpuobj *gpuobj)
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{
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struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
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struct nv50_gpuobj_node *node = gpuobj->node;
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int ret;
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ret = nouveau_vm_get(dev_priv->bar3_vm, gpuobj->size, 12,
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NV_MEM_ACCESS_RW, &node->vram->bar_vma);
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if (ret)
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return ret;
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nouveau_vm_map(&node->vram->bar_vma, node->vram);
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gpuobj->pinst = node->vram->bar_vma.offset;
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return 0;
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}
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void
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nv50_instmem_unmap(struct nouveau_gpuobj *gpuobj)
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{
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struct nv50_gpuobj_node *node = gpuobj->node;
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if (node->vram->bar_vma.node) {
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nouveau_vm_unmap(&node->vram->bar_vma);
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nouveau_vm_put(&node->vram->bar_vma);
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}
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}
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void
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nv50_instmem_flush(struct drm_device *dev)
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{
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nv_wr32(dev, 0x00330c, 0x00000001);
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if (!nv_wait(dev, 0x00330c, 0x00000002, 0x00000000))
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NV_ERROR(dev, "PRAMIN flush timeout\n");
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}
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void
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nv84_instmem_flush(struct drm_device *dev)
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{
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nv_wr32(dev, 0x070000, 0x00000001);
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if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000))
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NV_ERROR(dev, "PRAMIN flush timeout\n");
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}
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