mirror of https://gitee.com/openkylin/linux.git
507 lines
15 KiB
C
507 lines
15 KiB
C
/*
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* Copyright (C) 2012 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_fifo.h"
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#include "nouveau_util.h"
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#include "nouveau_ramht.h"
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#include "nouveau_software.h"
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static struct ramfc_desc {
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unsigned bits:6;
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unsigned ctxs:5;
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unsigned ctxp:8;
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unsigned regs:5;
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unsigned regp;
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} nv04_ramfc[] = {
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{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
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{ 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
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{ 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
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{ 16, 16, 0x08, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
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{ 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_STATE },
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{ 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
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{ 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_ENGINE },
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{ 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_PULL1 },
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{}
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};
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struct nv04_fifo_priv {
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struct nouveau_fifo_priv base;
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struct ramfc_desc *ramfc_desc;
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};
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struct nv04_fifo_chan {
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struct nouveau_fifo_chan base;
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struct nouveau_gpuobj *ramfc;
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};
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bool
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nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
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{
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int pull = nv_mask(dev, NV04_PFIFO_CACHE1_PULL0, 1, enable);
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if (!enable) {
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/* In some cases the PFIFO puller may be left in an
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* inconsistent state if you try to stop it when it's
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* busy translating handles. Sometimes you get a
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* PFIFO_CACHE_ERROR, sometimes it just fails silently
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* sending incorrect instance offsets to PGRAPH after
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* it's started up again. To avoid the latter we
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* invalidate the most recently calculated instance.
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*/
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if (!nv_wait(dev, NV04_PFIFO_CACHE1_PULL0,
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NV04_PFIFO_CACHE1_PULL0_HASH_BUSY, 0))
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NV_ERROR(dev, "Timeout idling the PFIFO puller.\n");
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if (nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0) &
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NV04_PFIFO_CACHE1_PULL0_HASH_FAILED)
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nv_wr32(dev, NV03_PFIFO_INTR_0,
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NV_PFIFO_INTR_CACHE_ERROR);
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nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
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}
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return pull & 1;
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}
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static int
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nv04_fifo_context_new(struct nouveau_channel *chan, int engine)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv04_fifo_priv *priv = nv_engine(dev, engine);
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struct nv04_fifo_chan *fctx;
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unsigned long flags;
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int ret;
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fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
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if (!fctx)
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return -ENOMEM;
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/* map channel control registers */
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chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
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NV03_USER(chan->id), PAGE_SIZE);
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if (!chan->user) {
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ret = -ENOMEM;
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goto error;
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}
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/* initialise default fifo context */
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ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramfc->pinst +
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chan->id * 32, ~0, 32,
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NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
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if (ret)
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goto error;
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nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base);
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nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base);
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nv_wo32(fctx->ramfc, 0x08, chan->pushbuf->pinst >> 4);
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nv_wo32(fctx->ramfc, 0x0c, 0x00000000);
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nv_wo32(fctx->ramfc, 0x10, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
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#ifdef __BIG_ENDIAN
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NV_PFIFO_CACHE1_BIG_ENDIAN |
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#endif
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NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
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nv_wo32(fctx->ramfc, 0x14, 0x00000000);
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nv_wo32(fctx->ramfc, 0x18, 0x00000000);
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nv_wo32(fctx->ramfc, 0x1c, 0x00000000);
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/* enable dma mode on the channel */
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_mask(dev, NV04_PFIFO_MODE, (1 << chan->id), (1 << chan->id));
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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error:
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if (ret)
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priv->base.base.context_del(chan, engine);
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return ret;
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}
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void
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nv04_fifo_context_del(struct nouveau_channel *chan, int engine)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv04_fifo_priv *priv = nv_engine(chan->dev, engine);
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struct nv04_fifo_chan *fctx = chan->engctx[engine];
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struct ramfc_desc *c = priv->ramfc_desc;
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unsigned long flags;
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int chid;
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/* prevent fifo context switches */
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_wr32(dev, NV03_PFIFO_CACHES, 0);
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/* if this channel is active, replace it with a null context */
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chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & priv->base.channels;
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if (chid == chan->id) {
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nv_mask(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
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nv_mask(dev, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
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do {
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u32 mask = ((1ULL << c->bits) - 1) << c->regs;
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nv_mask(dev, c->regp, mask, 0x00000000);
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} while ((++c)->bits);
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nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, priv->base.channels);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
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}
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/* restore normal operation, after disabling dma mode */
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nv_mask(dev, NV04_PFIFO_MODE, 1 << chan->id, 0);
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nv_wr32(dev, NV03_PFIFO_CACHES, 1);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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/* clean up */
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nouveau_gpuobj_ref(NULL, &fctx->ramfc);
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nouveau_gpuobj_ref(NULL, &chan->ramfc); /*XXX: nv40 */
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if (chan->user) {
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iounmap(chan->user);
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chan->user = NULL;
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}
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}
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int
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nv04_fifo_init(struct drm_device *dev, int engine)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv04_fifo_priv *priv = nv_engine(dev, engine);
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int i;
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nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, 0);
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nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, NV_PMC_ENABLE_PFIFO);
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nv_wr32(dev, NV04_PFIFO_DELAY_0, 0x000000ff);
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nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
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nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
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((dev_priv->ramht->bits - 9) << 16) |
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(dev_priv->ramht->gpuobj->pinst >> 8));
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nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
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nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, priv->base.channels);
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nv_wr32(dev, NV03_PFIFO_INTR_0, 0xffffffff);
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nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xffffffff);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
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nv_wr32(dev, NV03_PFIFO_CACHES, 1);
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for (i = 0; i < priv->base.channels; i++) {
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if (dev_priv->channels.ptr[i])
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nv_mask(dev, NV04_PFIFO_MODE, (1 << i), (1 << i));
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}
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return 0;
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}
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int
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nv04_fifo_fini(struct drm_device *dev, int engine, bool suspend)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv04_fifo_priv *priv = nv_engine(dev, engine);
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struct nouveau_channel *chan;
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int chid;
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/* prevent context switches and halt fifo operation */
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nv_wr32(dev, NV03_PFIFO_CACHES, 0);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 0);
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/* store current fifo context in ramfc */
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chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & priv->base.channels;
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chan = dev_priv->channels.ptr[chid];
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if (suspend && chid != priv->base.channels && chan) {
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struct nv04_fifo_chan *fctx = chan->engctx[engine];
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struct nouveau_gpuobj *ctx = fctx->ramfc;
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struct ramfc_desc *c = priv->ramfc_desc;
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do {
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u32 rm = ((1ULL << c->bits) - 1) << c->regs;
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u32 cm = ((1ULL << c->bits) - 1) << c->ctxs;
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u32 rv = (nv_rd32(dev, c->regp) & rm) >> c->regs;
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u32 cv = (nv_ro32(ctx, c->ctxp) & ~cm);
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nv_wo32(ctx, c->ctxp, cv | (rv << c->ctxs));
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} while ((++c)->bits);
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}
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nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0x00000000);
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return 0;
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}
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static bool
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nouveau_fifo_swmthd(struct drm_device *dev, u32 chid, u32 addr, u32 data)
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{
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struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan = NULL;
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struct nouveau_gpuobj *obj;
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unsigned long flags;
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const int subc = (addr >> 13) & 0x7;
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const int mthd = addr & 0x1ffc;
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bool handled = false;
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u32 engine;
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spin_lock_irqsave(&dev_priv->channels.lock, flags);
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if (likely(chid >= 0 && chid < pfifo->channels))
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chan = dev_priv->channels.ptr[chid];
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if (unlikely(!chan))
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goto out;
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switch (mthd) {
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case 0x0000: /* bind object to subchannel */
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obj = nouveau_ramht_find(chan, data);
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if (unlikely(!obj || obj->engine != NVOBJ_ENGINE_SW))
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break;
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engine = 0x0000000f << (subc * 4);
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nv_mask(dev, NV04_PFIFO_CACHE1_ENGINE, engine, 0x00000000);
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handled = true;
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break;
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default:
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engine = nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE);
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if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
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break;
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if (!nouveau_gpuobj_mthd_call(chan, nouveau_software_class(dev),
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mthd, data))
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handled = true;
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break;
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}
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out:
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spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
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return handled;
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}
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static const char *nv_dma_state_err(u32 state)
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{
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static const char * const desc[] = {
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"NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE",
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"INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK"
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};
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return desc[(state >> 29) & 0x7];
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}
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void
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nv04_fifo_isr(struct drm_device *dev)
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{
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struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t status, reassign;
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int cnt = 0;
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reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1;
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while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
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uint32_t chid, get;
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nv_wr32(dev, NV03_PFIFO_CACHES, 0);
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chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & pfifo->channels;
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get = nv_rd32(dev, NV03_PFIFO_CACHE1_GET);
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if (status & NV_PFIFO_INTR_CACHE_ERROR) {
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uint32_t mthd, data;
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int ptr;
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/* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
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* wrapping on my G80 chips, but CACHE1 isn't big
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* enough for this much data.. Tests show that it
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* wraps around to the start at GET=0x800.. No clue
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* as to why..
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*/
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ptr = (get & 0x7ff) >> 2;
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if (dev_priv->card_type < NV_40) {
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mthd = nv_rd32(dev,
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NV04_PFIFO_CACHE1_METHOD(ptr));
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data = nv_rd32(dev,
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NV04_PFIFO_CACHE1_DATA(ptr));
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} else {
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mthd = nv_rd32(dev,
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NV40_PFIFO_CACHE1_METHOD(ptr));
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data = nv_rd32(dev,
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NV40_PFIFO_CACHE1_DATA(ptr));
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}
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if (!nouveau_fifo_swmthd(dev, chid, mthd, data)) {
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NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d "
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"Mthd 0x%04x Data 0x%08x\n",
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chid, (mthd >> 13) & 7, mthd & 0x1ffc,
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data);
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}
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
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nv_wr32(dev, NV03_PFIFO_INTR_0,
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NV_PFIFO_INTR_CACHE_ERROR);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
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nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1);
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nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
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nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1);
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nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH,
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nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
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status &= ~NV_PFIFO_INTR_CACHE_ERROR;
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}
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if (status & NV_PFIFO_INTR_DMA_PUSHER) {
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u32 dma_get = nv_rd32(dev, 0x003244);
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u32 dma_put = nv_rd32(dev, 0x003240);
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u32 push = nv_rd32(dev, 0x003220);
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u32 state = nv_rd32(dev, 0x003228);
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if (dev_priv->card_type == NV_50) {
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u32 ho_get = nv_rd32(dev, 0x003328);
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u32 ho_put = nv_rd32(dev, 0x003320);
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u32 ib_get = nv_rd32(dev, 0x003334);
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u32 ib_put = nv_rd32(dev, 0x003330);
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if (nouveau_ratelimit())
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NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
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"Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
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"State 0x%08x (err: %s) Push 0x%08x\n",
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chid, ho_get, dma_get, ho_put,
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dma_put, ib_get, ib_put, state,
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nv_dma_state_err(state),
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push);
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/* METHOD_COUNT, in DMA_STATE on earlier chipsets */
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nv_wr32(dev, 0x003364, 0x00000000);
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if (dma_get != dma_put || ho_get != ho_put) {
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nv_wr32(dev, 0x003244, dma_put);
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nv_wr32(dev, 0x003328, ho_put);
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} else
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if (ib_get != ib_put) {
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nv_wr32(dev, 0x003334, ib_put);
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}
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} else {
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NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
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"Put 0x%08x State 0x%08x (err: %s) Push 0x%08x\n",
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chid, dma_get, dma_put, state,
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nv_dma_state_err(state), push);
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if (dma_get != dma_put)
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nv_wr32(dev, 0x003244, dma_put);
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}
|
|
|
|
nv_wr32(dev, 0x003228, 0x00000000);
|
|
nv_wr32(dev, 0x003220, 0x00000001);
|
|
nv_wr32(dev, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
|
|
status &= ~NV_PFIFO_INTR_DMA_PUSHER;
|
|
}
|
|
|
|
if (status & NV_PFIFO_INTR_SEMAPHORE) {
|
|
uint32_t sem;
|
|
|
|
status &= ~NV_PFIFO_INTR_SEMAPHORE;
|
|
nv_wr32(dev, NV03_PFIFO_INTR_0,
|
|
NV_PFIFO_INTR_SEMAPHORE);
|
|
|
|
sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
|
|
nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
|
|
|
|
nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
|
|
nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
|
|
}
|
|
|
|
if (dev_priv->card_type == NV_50) {
|
|
if (status & 0x00000010) {
|
|
nv50_fb_vm_trap(dev, nouveau_ratelimit());
|
|
status &= ~0x00000010;
|
|
nv_wr32(dev, 0x002100, 0x00000010);
|
|
}
|
|
}
|
|
|
|
if (status) {
|
|
if (nouveau_ratelimit())
|
|
NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
|
|
status, chid);
|
|
nv_wr32(dev, NV03_PFIFO_INTR_0, status);
|
|
status = 0;
|
|
}
|
|
|
|
nv_wr32(dev, NV03_PFIFO_CACHES, reassign);
|
|
}
|
|
|
|
if (status) {
|
|
NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt);
|
|
nv_wr32(dev, 0x2140, 0);
|
|
nv_wr32(dev, 0x140, 0);
|
|
}
|
|
|
|
nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
|
|
}
|
|
|
|
void
|
|
nv04_fifo_destroy(struct drm_device *dev, int engine)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nv04_fifo_priv *priv = nv_engine(dev, engine);
|
|
|
|
nouveau_irq_unregister(dev, 8);
|
|
|
|
dev_priv->eng[engine] = NULL;
|
|
kfree(priv);
|
|
}
|
|
|
|
int
|
|
nv04_fifo_create(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nv04_fifo_priv *priv;
|
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->base.base.destroy = nv04_fifo_destroy;
|
|
priv->base.base.init = nv04_fifo_init;
|
|
priv->base.base.fini = nv04_fifo_fini;
|
|
priv->base.base.context_new = nv04_fifo_context_new;
|
|
priv->base.base.context_del = nv04_fifo_context_del;
|
|
priv->base.channels = 15;
|
|
priv->ramfc_desc = nv04_ramfc;
|
|
dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;
|
|
|
|
nouveau_irq_register(dev, 8, nv04_fifo_isr);
|
|
return 0;
|
|
}
|