mirror of https://gitee.com/openkylin/linux.git
764 lines
19 KiB
C
764 lines
19 KiB
C
/*
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* Copyright (C) 2014 STMicroelectronics (R&D) Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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/*
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* Authors:
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* Stephen Gallimore <stephen.gallimore@st.com>,
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* Pankaj Dev <pankaj.dev@st.com>.
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*/
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#include <linux/slab.h>
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#include <linux/of_address.h>
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#include <linux/clk-provider.h>
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#include "clkgen.h"
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static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
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/*
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* Common PLL configuration register bits for PLL800 and PLL1600 C65
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*/
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#define C65_MDIV_PLL800_MASK (0xff)
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#define C65_MDIV_PLL1600_MASK (0x7)
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#define C65_NDIV_MASK (0xff)
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#define C65_PDIV_MASK (0x7)
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/*
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* PLL configuration register bits for PLL3200 C32
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*/
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#define C32_NDIV_MASK (0xff)
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#define C32_IDF_MASK (0x7)
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#define C32_ODF_MASK (0x3f)
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#define C32_LDF_MASK (0x7f)
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#define C32_MAX_ODFS (4)
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struct clkgen_pll_data {
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struct clkgen_field pdn_status;
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struct clkgen_field locked_status;
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struct clkgen_field mdiv;
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struct clkgen_field ndiv;
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struct clkgen_field pdiv;
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struct clkgen_field idf;
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struct clkgen_field ldf;
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unsigned int num_odfs;
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struct clkgen_field odf[C32_MAX_ODFS];
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struct clkgen_field odf_gate[C32_MAX_ODFS];
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const struct clk_ops *ops;
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};
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static const struct clk_ops st_pll1600c65_ops;
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static const struct clk_ops st_pll800c65_ops;
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static const struct clk_ops stm_pll3200c32_ops;
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static const struct clk_ops st_pll1200c32_ops;
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static const struct clkgen_pll_data st_pll1600c65_ax = {
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.pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
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.locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
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.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
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.ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
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.ops = &st_pll1600c65_ops
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};
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static const struct clkgen_pll_data st_pll800c65_ax = {
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.pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
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.locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
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.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
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.ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
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.pdiv = CLKGEN_FIELD(0x0, C65_PDIV_MASK, 16),
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.ops = &st_pll800c65_ops
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};
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static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
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.pdn_status = CLKGEN_FIELD(0x0, 0x1, 31),
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.locked_status = CLKGEN_FIELD(0x4, 0x1, 31),
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.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
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.idf = CLKGEN_FIELD(0x4, C32_IDF_MASK, 0x0),
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.num_odfs = 4,
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.odf = { CLKGEN_FIELD(0x54, C32_ODF_MASK, 4),
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CLKGEN_FIELD(0x54, C32_ODF_MASK, 10),
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CLKGEN_FIELD(0x54, C32_ODF_MASK, 16),
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CLKGEN_FIELD(0x54, C32_ODF_MASK, 22) },
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.odf_gate = { CLKGEN_FIELD(0x54, 0x1, 0),
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CLKGEN_FIELD(0x54, 0x1, 1),
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CLKGEN_FIELD(0x54, 0x1, 2),
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CLKGEN_FIELD(0x54, 0x1, 3) },
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.ops = &stm_pll3200c32_ops,
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};
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static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
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.pdn_status = CLKGEN_FIELD(0xC, 0x1, 31),
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.locked_status = CLKGEN_FIELD(0x10, 0x1, 31),
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.ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
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.idf = CLKGEN_FIELD(0x10, C32_IDF_MASK, 0x0),
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.num_odfs = 4,
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.odf = { CLKGEN_FIELD(0x58, C32_ODF_MASK, 4),
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CLKGEN_FIELD(0x58, C32_ODF_MASK, 10),
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CLKGEN_FIELD(0x58, C32_ODF_MASK, 16),
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CLKGEN_FIELD(0x58, C32_ODF_MASK, 22) },
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.odf_gate = { CLKGEN_FIELD(0x58, 0x1, 0),
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CLKGEN_FIELD(0x58, 0x1, 1),
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CLKGEN_FIELD(0x58, 0x1, 2),
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CLKGEN_FIELD(0x58, 0x1, 3) },
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.ops = &stm_pll3200c32_ops,
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};
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/* 415 specific */
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static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
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.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
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.locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
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.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
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.idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 22),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 3) },
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.odf_gate = { CLKGEN_FIELD(0x0, 0x1, 28) },
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.ops = &stm_pll3200c32_ops,
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};
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static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
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.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
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.locked_status = CLKGEN_FIELD(0x100, 0x1, 0),
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.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
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.idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
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.num_odfs = 2,
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.odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8),
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CLKGEN_FIELD(0x8, C32_ODF_MASK, 14) },
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.odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28),
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CLKGEN_FIELD(0x4, 0x1, 29) },
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.ops = &stm_pll3200c32_ops,
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};
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static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
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.pdn_status = CLKGEN_FIELD(0x144, 0x1, 3),
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.locked_status = CLKGEN_FIELD(0x168, 0x1, 0),
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.ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
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.idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
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.num_odfs = 0,
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.odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 10) },
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.ops = &st_pll1200c32_ops,
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};
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/* 416 specific */
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static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
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.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
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.locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
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.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
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.idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8) },
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.odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28) },
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.ops = &stm_pll3200c32_ops,
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};
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static const struct clkgen_pll_data st_pll3200c32_ddr_416 = {
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.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
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.locked_status = CLKGEN_FIELD(0x10C, 0x1, 0),
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.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
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.idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
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.num_odfs = 2,
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.odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8),
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CLKGEN_FIELD(0x8, C32_ODF_MASK, 14) },
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.odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28),
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CLKGEN_FIELD(0x4, 0x1, 29) },
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.ops = &stm_pll3200c32_ops,
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};
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static const struct clkgen_pll_data st_pll1200c32_gpu_416 = {
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.pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3),
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.locked_status = CLKGEN_FIELD(0x90C, 0x1, 0),
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.ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
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.idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
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.num_odfs = 0,
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.odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 10) },
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.ops = &st_pll1200c32_ops,
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};
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static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
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/* 407 A0 */
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.pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
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.locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
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.ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
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.idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
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.odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
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.ops = &stm_pll3200c32_ops,
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};
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static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
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/* 407 C0 PLL0 */
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.pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
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.locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
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.ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
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.idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
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.odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
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.ops = &stm_pll3200c32_ops,
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};
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static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
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/* 407 C0 PLL1 */
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.pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
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.locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
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.ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
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.idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
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.odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
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.ops = &stm_pll3200c32_ops,
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};
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static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
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/* 407 A9 */
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.pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
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.locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
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.ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
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.idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
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.odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
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.ops = &stm_pll3200c32_ops,
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};
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/**
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* DOC: Clock Generated by PLL, rate set and enabled by bootloader
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parent is (un)prepared
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* enable - clk_enable/disable only ensures parent is enabled
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* rate - rate is fixed. No clk_set_rate support
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* parent - fixed parent. No clk_set_parent support
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*/
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/**
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* PLL clock that is integrated in the ClockGenA instances on the STiH415
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* and STiH416.
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*
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* @hw: handle between common and hardware-specific interfaces.
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* @type: PLL instance type.
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* @regs_base: base of the PLL configuration register(s).
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*
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*/
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struct clkgen_pll {
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struct clk_hw hw;
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struct clkgen_pll_data *data;
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void __iomem *regs_base;
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};
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#define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
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static int clkgen_pll_is_locked(struct clk_hw *hw)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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u32 locked = CLKGEN_READ(pll, locked_status);
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return !!locked;
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}
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static int clkgen_pll_is_enabled(struct clk_hw *hw)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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u32 poweroff = CLKGEN_READ(pll, pdn_status);
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return !poweroff;
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}
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static unsigned long recalc_stm_pll800c65(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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unsigned long mdiv, ndiv, pdiv;
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unsigned long rate;
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uint64_t res;
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if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
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return 0;
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pdiv = CLKGEN_READ(pll, pdiv);
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mdiv = CLKGEN_READ(pll, mdiv);
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ndiv = CLKGEN_READ(pll, ndiv);
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if (!mdiv)
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mdiv++; /* mdiv=0 or 1 => MDIV=1 */
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res = (uint64_t)2 * (uint64_t)parent_rate * (uint64_t)ndiv;
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rate = (unsigned long)div64_u64(res, mdiv * (1 << pdiv));
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pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
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return rate;
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}
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static unsigned long recalc_stm_pll1600c65(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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unsigned long mdiv, ndiv;
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unsigned long rate;
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if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
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return 0;
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mdiv = CLKGEN_READ(pll, mdiv);
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ndiv = CLKGEN_READ(pll, ndiv);
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if (!mdiv)
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mdiv = 1;
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/* Note: input is divided by 1000 to avoid overflow */
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rate = ((2 * (parent_rate / 1000) * ndiv) / mdiv) * 1000;
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pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
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return rate;
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}
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static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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unsigned long ndiv, idf;
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unsigned long rate = 0;
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if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
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return 0;
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ndiv = CLKGEN_READ(pll, ndiv);
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idf = CLKGEN_READ(pll, idf);
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if (idf)
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/* Note: input is divided to avoid overflow */
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rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;
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pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
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return rate;
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}
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static unsigned long recalc_stm_pll1200c32(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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unsigned long odf, ldf, idf;
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unsigned long rate;
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if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
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return 0;
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odf = CLKGEN_READ(pll, odf[0]);
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ldf = CLKGEN_READ(pll, ldf);
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idf = CLKGEN_READ(pll, idf);
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if (!idf) /* idf==0 means 1 */
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idf = 1;
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if (!odf) /* odf==0 means 1 */
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odf = 1;
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/* Note: input is divided by 1000 to avoid overflow */
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rate = (((parent_rate / 1000) * ldf) / (odf * idf)) * 1000;
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pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
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return rate;
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}
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static const struct clk_ops st_pll1600c65_ops = {
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.is_enabled = clkgen_pll_is_enabled,
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.recalc_rate = recalc_stm_pll1600c65,
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};
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static const struct clk_ops st_pll800c65_ops = {
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.is_enabled = clkgen_pll_is_enabled,
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.recalc_rate = recalc_stm_pll800c65,
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};
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static const struct clk_ops stm_pll3200c32_ops = {
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.is_enabled = clkgen_pll_is_enabled,
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.recalc_rate = recalc_stm_pll3200c32,
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};
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static const struct clk_ops st_pll1200c32_ops = {
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.is_enabled = clkgen_pll_is_enabled,
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.recalc_rate = recalc_stm_pll1200c32,
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};
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static struct clk * __init clkgen_pll_register(const char *parent_name,
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struct clkgen_pll_data *pll_data,
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void __iomem *reg,
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const char *clk_name)
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{
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struct clkgen_pll *pll;
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struct clk *clk;
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struct clk_init_data init;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = clk_name;
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init.ops = pll_data->ops;
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init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pll->data = pll_data;
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pll->regs_base = reg;
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pll->hw.init = &init;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk)) {
|
|
kfree(pll);
|
|
return clk;
|
|
}
|
|
|
|
pr_debug("%s: parent %s rate %lu\n",
|
|
__clk_get_name(clk),
|
|
__clk_get_name(clk_get_parent(clk)),
|
|
clk_get_rate(clk));
|
|
|
|
return clk;
|
|
}
|
|
|
|
static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name,
|
|
const char *clk_name)
|
|
{
|
|
struct clk *clk;
|
|
|
|
clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 1, 2);
|
|
if (IS_ERR(clk))
|
|
return clk;
|
|
|
|
pr_debug("%s: parent %s rate %lu\n",
|
|
__clk_get_name(clk),
|
|
__clk_get_name(clk_get_parent(clk)),
|
|
clk_get_rate(clk));
|
|
return clk;
|
|
}
|
|
|
|
static void __iomem * __init clkgen_get_register_base(
|
|
struct device_node *np)
|
|
{
|
|
struct device_node *pnode;
|
|
void __iomem *reg = NULL;
|
|
|
|
pnode = of_get_parent(np);
|
|
if (!pnode)
|
|
return NULL;
|
|
|
|
reg = of_iomap(pnode, 0);
|
|
|
|
of_node_put(pnode);
|
|
return reg;
|
|
}
|
|
|
|
#define CLKGENAx_PLL0_OFFSET 0x0
|
|
#define CLKGENAx_PLL1_OFFSET 0x4
|
|
|
|
static void __init clkgena_c65_pll_setup(struct device_node *np)
|
|
{
|
|
const int num_pll_outputs = 3;
|
|
struct clk_onecell_data *clk_data;
|
|
const char *parent_name;
|
|
void __iomem *reg;
|
|
const char *clk_name;
|
|
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
if (!parent_name)
|
|
return;
|
|
|
|
reg = clkgen_get_register_base(np);
|
|
if (!reg)
|
|
return;
|
|
|
|
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
|
if (!clk_data)
|
|
return;
|
|
|
|
clk_data->clk_num = num_pll_outputs;
|
|
clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
|
|
GFP_KERNEL);
|
|
|
|
if (!clk_data->clks)
|
|
goto err;
|
|
|
|
if (of_property_read_string_index(np, "clock-output-names",
|
|
0, &clk_name))
|
|
goto err;
|
|
|
|
/*
|
|
* PLL0 HS (high speed) output
|
|
*/
|
|
clk_data->clks[0] = clkgen_pll_register(parent_name,
|
|
(struct clkgen_pll_data *) &st_pll1600c65_ax,
|
|
reg + CLKGENAx_PLL0_OFFSET, clk_name);
|
|
|
|
if (IS_ERR(clk_data->clks[0]))
|
|
goto err;
|
|
|
|
if (of_property_read_string_index(np, "clock-output-names",
|
|
1, &clk_name))
|
|
goto err;
|
|
|
|
/*
|
|
* PLL0 LS (low speed) output, which is a fixed divide by 2 of the
|
|
* high speed output.
|
|
*/
|
|
clk_data->clks[1] = clkgen_c65_lsdiv_register(__clk_get_name
|
|
(clk_data->clks[0]),
|
|
clk_name);
|
|
|
|
if (IS_ERR(clk_data->clks[1]))
|
|
goto err;
|
|
|
|
if (of_property_read_string_index(np, "clock-output-names",
|
|
2, &clk_name))
|
|
goto err;
|
|
|
|
/*
|
|
* PLL1 output
|
|
*/
|
|
clk_data->clks[2] = clkgen_pll_register(parent_name,
|
|
(struct clkgen_pll_data *) &st_pll800c65_ax,
|
|
reg + CLKGENAx_PLL1_OFFSET, clk_name);
|
|
|
|
if (IS_ERR(clk_data->clks[2]))
|
|
goto err;
|
|
|
|
of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
|
|
return;
|
|
|
|
err:
|
|
kfree(clk_data->clks);
|
|
kfree(clk_data);
|
|
}
|
|
CLK_OF_DECLARE(clkgena_c65_plls,
|
|
"st,clkgena-plls-c65", clkgena_c65_pll_setup);
|
|
|
|
static struct clk * __init clkgen_odf_register(const char *parent_name,
|
|
void __iomem *reg,
|
|
struct clkgen_pll_data *pll_data,
|
|
int odf,
|
|
spinlock_t *odf_lock,
|
|
const char *odf_name)
|
|
{
|
|
struct clk *clk;
|
|
unsigned long flags;
|
|
struct clk_gate *gate;
|
|
struct clk_divider *div;
|
|
|
|
flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
|
|
|
|
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
|
if (!gate)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
gate->flags = CLK_GATE_SET_TO_DISABLE;
|
|
gate->reg = reg + pll_data->odf_gate[odf].offset;
|
|
gate->bit_idx = pll_data->odf_gate[odf].shift;
|
|
gate->lock = odf_lock;
|
|
|
|
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
|
if (!div) {
|
|
kfree(gate);
|
|
return ERR_PTR(-ENOMEM);
|
|
}
|
|
|
|
div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
|
|
div->reg = reg + pll_data->odf[odf].offset;
|
|
div->shift = pll_data->odf[odf].shift;
|
|
div->width = fls(pll_data->odf[odf].mask);
|
|
div->lock = odf_lock;
|
|
|
|
clk = clk_register_composite(NULL, odf_name, &parent_name, 1,
|
|
NULL, NULL,
|
|
&div->hw, &clk_divider_ops,
|
|
&gate->hw, &clk_gate_ops,
|
|
flags);
|
|
if (IS_ERR(clk))
|
|
return clk;
|
|
|
|
pr_debug("%s: parent %s rate %lu\n",
|
|
__clk_get_name(clk),
|
|
__clk_get_name(clk_get_parent(clk)),
|
|
clk_get_rate(clk));
|
|
return clk;
|
|
}
|
|
|
|
static const struct of_device_id c32_pll_of_match[] = {
|
|
{
|
|
.compatible = "st,plls-c32-a1x-0",
|
|
.data = &st_pll3200c32_a1x_0,
|
|
},
|
|
{
|
|
.compatible = "st,plls-c32-a1x-1",
|
|
.data = &st_pll3200c32_a1x_1,
|
|
},
|
|
{
|
|
.compatible = "st,stih415-plls-c32-a9",
|
|
.data = &st_pll3200c32_a9_415,
|
|
},
|
|
{
|
|
.compatible = "st,stih415-plls-c32-ddr",
|
|
.data = &st_pll3200c32_ddr_415,
|
|
},
|
|
{
|
|
.compatible = "st,stih416-plls-c32-a9",
|
|
.data = &st_pll3200c32_a9_416,
|
|
},
|
|
{
|
|
.compatible = "st,stih416-plls-c32-ddr",
|
|
.data = &st_pll3200c32_ddr_416,
|
|
},
|
|
{
|
|
.compatible = "st,stih407-plls-c32-a0",
|
|
.data = &st_pll3200c32_407_a0,
|
|
},
|
|
{
|
|
.compatible = "st,stih407-plls-c32-c0_0",
|
|
.data = &st_pll3200c32_407_c0_0,
|
|
},
|
|
{
|
|
.compatible = "st,stih407-plls-c32-c0_1",
|
|
.data = &st_pll3200c32_407_c0_1,
|
|
},
|
|
{
|
|
.compatible = "st,stih407-plls-c32-a9",
|
|
.data = &st_pll3200c32_407_a9,
|
|
},
|
|
{}
|
|
};
|
|
|
|
static void __init clkgen_c32_pll_setup(struct device_node *np)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct clk *clk;
|
|
const char *parent_name, *pll_name;
|
|
void __iomem *pll_base;
|
|
int num_odfs, odf;
|
|
struct clk_onecell_data *clk_data;
|
|
struct clkgen_pll_data *data;
|
|
|
|
match = of_match_node(c32_pll_of_match, np);
|
|
if (!match) {
|
|
pr_err("%s: No matching data\n", __func__);
|
|
return;
|
|
}
|
|
|
|
data = (struct clkgen_pll_data *) match->data;
|
|
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
if (!parent_name)
|
|
return;
|
|
|
|
pll_base = clkgen_get_register_base(np);
|
|
if (!pll_base)
|
|
return;
|
|
|
|
clk = clkgen_pll_register(parent_name, data, pll_base, np->name);
|
|
if (IS_ERR(clk))
|
|
return;
|
|
|
|
pll_name = __clk_get_name(clk);
|
|
|
|
num_odfs = data->num_odfs;
|
|
|
|
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
|
if (!clk_data)
|
|
return;
|
|
|
|
clk_data->clk_num = num_odfs;
|
|
clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
|
|
GFP_KERNEL);
|
|
|
|
if (!clk_data->clks)
|
|
goto err;
|
|
|
|
for (odf = 0; odf < num_odfs; odf++) {
|
|
struct clk *clk;
|
|
const char *clk_name;
|
|
|
|
if (of_property_read_string_index(np, "clock-output-names",
|
|
odf, &clk_name))
|
|
return;
|
|
|
|
clk = clkgen_odf_register(pll_name, pll_base, data,
|
|
odf, &clkgena_c32_odf_lock, clk_name);
|
|
if (IS_ERR(clk))
|
|
goto err;
|
|
|
|
clk_data->clks[odf] = clk;
|
|
}
|
|
|
|
of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
|
|
return;
|
|
|
|
err:
|
|
kfree(pll_name);
|
|
kfree(clk_data->clks);
|
|
kfree(clk_data);
|
|
}
|
|
CLK_OF_DECLARE(clkgen_c32_pll, "st,clkgen-plls-c32", clkgen_c32_pll_setup);
|
|
|
|
static const struct of_device_id c32_gpu_pll_of_match[] = {
|
|
{
|
|
.compatible = "st,stih415-gpu-pll-c32",
|
|
.data = &st_pll1200c32_gpu_415,
|
|
},
|
|
{
|
|
.compatible = "st,stih416-gpu-pll-c32",
|
|
.data = &st_pll1200c32_gpu_416,
|
|
},
|
|
{}
|
|
};
|
|
|
|
static void __init clkgengpu_c32_pll_setup(struct device_node *np)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct clk *clk;
|
|
const char *parent_name;
|
|
void __iomem *reg;
|
|
const char *clk_name;
|
|
struct clkgen_pll_data *data;
|
|
|
|
match = of_match_node(c32_gpu_pll_of_match, np);
|
|
if (!match) {
|
|
pr_err("%s: No matching data\n", __func__);
|
|
return;
|
|
}
|
|
|
|
data = (struct clkgen_pll_data *)match->data;
|
|
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
if (!parent_name)
|
|
return;
|
|
|
|
reg = clkgen_get_register_base(np);
|
|
if (!reg)
|
|
return;
|
|
|
|
if (of_property_read_string_index(np, "clock-output-names",
|
|
0, &clk_name))
|
|
return;
|
|
|
|
/*
|
|
* PLL 1200MHz output
|
|
*/
|
|
clk = clkgen_pll_register(parent_name, data, reg, clk_name);
|
|
|
|
if (!IS_ERR(clk))
|
|
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
|
|
|
return;
|
|
}
|
|
CLK_OF_DECLARE(clkgengpu_c32_pll,
|
|
"st,clkgengpu-pll-c32", clkgengpu_c32_pll_setup);
|