mirror of https://gitee.com/openkylin/linux.git
67 lines
2.3 KiB
Plaintext
67 lines
2.3 KiB
Plaintext
* Cadence PCIe host controller
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This PCIe controller inherits the base properties defined in
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host-generic-pci.txt.
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Required properties:
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- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.
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- reg: Should contain the controller register base address, PCIe configuration
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window base address, and AXI interface region base address respectively.
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- reg-names: Must be "reg", "cfg" and "mem" respectively.
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- #address-cells: Set to <3>
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- #size-cells: Set to <2>
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- device_type: Set to "pci"
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- ranges: Ranges for the PCI memory and I/O regions
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- #interrupt-cells: Set to <1>
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- interrupt-map-mask and interrupt-map: Standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers.
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Optional properties:
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- cdns,max-outbound-regions: Set to maximum number of outbound regions
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(default 32)
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- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the
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number of least significant bits kept during inbound (PCIe -> AXI) address
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translations (default 32)
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- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
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- device-id: The PCI device ID (16 bits, default is design dependent)
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- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
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than one in the list. If only one PHY listed it must manage all lanes.
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- phy-names: List of names to identify the PHY.
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Example:
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pcie@fb000000 {
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compatible = "cdns,cdns-pcie-host";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xff>;
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linux,pci-domain = <0>;
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cdns,max-outbound-regions = <16>;
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cdns,no-bar-match-nbits = <32>;
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vendor-id = /bits/ 16 <0x17cd>;
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device-id = /bits/ 16 <0x0200>;
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reg = <0x0 0xfb000000 0x0 0x01000000>,
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<0x0 0x41000000 0x0 0x00001000>,
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<0x0 0x40000000 0x0 0x04000000>;
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reg-names = "reg", "cfg", "mem";
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ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
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<0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
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#interrupt-cells = <0x1>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1
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0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1
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0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1
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0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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msi-parent = <&its_pci>;
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phys = <&pcie_phy0>;
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phy-names = "pcie-phy";
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};
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