mirror of https://gitee.com/openkylin/linux.git
434 lines
10 KiB
C
434 lines
10 KiB
C
/*
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* Copyright 2011 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/types.h>
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#include <linux/threads.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/debugfs.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/seq_file.h>
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <asm/prom.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/machdep.h>
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#include <asm/irq.h>
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#include <asm/errno.h>
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#include <asm/rtas.h>
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#include <asm/xics.h>
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#include <asm/firmware.h>
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/* Globals common to all ICP/ICS implementations */
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const struct icp_ops *icp_ops;
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unsigned int xics_default_server = 0xff;
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unsigned int xics_default_distrib_server = 0;
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unsigned int xics_interrupt_server_size = 8;
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DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
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struct irq_domain *xics_host;
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static LIST_HEAD(ics_list);
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void xics_update_irq_servers(void)
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{
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int i, j;
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struct device_node *np;
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u32 ilen;
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const __be32 *ireg;
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u32 hcpuid;
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/* Find the server numbers for the boot cpu. */
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np = of_get_cpu_node(boot_cpuid, NULL);
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BUG_ON(!np);
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hcpuid = get_hard_smp_processor_id(boot_cpuid);
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xics_default_server = xics_default_distrib_server = hcpuid;
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pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server);
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ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
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if (!ireg) {
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of_node_put(np);
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return;
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}
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i = ilen / sizeof(int);
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/* Global interrupt distribution server is specified in the last
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* entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
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* entry fom this property for current boot cpu id and use it as
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* default distribution server
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*/
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for (j = 0; j < i; j += 2) {
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if (be32_to_cpu(ireg[j]) == hcpuid) {
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xics_default_distrib_server = be32_to_cpu(ireg[j+1]);
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break;
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}
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}
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pr_devel("xics: xics_default_distrib_server = 0x%x\n",
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xics_default_distrib_server);
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of_node_put(np);
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}
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/* GIQ stuff, currently only supported on RTAS setups, will have
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* to be sorted properly for bare metal
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*/
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void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
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{
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#ifdef CONFIG_PPC_RTAS
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int index;
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int status;
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if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
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return;
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index = (1UL << xics_interrupt_server_size) - 1 - gserver;
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status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
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WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
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GLOBAL_INTERRUPT_QUEUE, index, join, status);
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#endif
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}
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void xics_setup_cpu(void)
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{
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icp_ops->set_priority(LOWEST_PRIORITY);
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xics_set_cpu_giq(xics_default_distrib_server, 1);
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}
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void xics_mask_unknown_vec(unsigned int vec)
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{
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struct ics *ics;
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pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec);
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list_for_each_entry(ics, &ics_list, link)
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ics->mask_unknown(ics, vec);
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}
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#ifdef CONFIG_SMP
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static void xics_request_ipi(void)
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{
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unsigned int ipi;
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ipi = irq_create_mapping(xics_host, XICS_IPI);
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BUG_ON(ipi == NO_IRQ);
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/*
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* IPIs are marked IRQF_PERCPU. The handler was set in map.
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*/
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BUG_ON(request_irq(ipi, icp_ops->ipi_action,
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IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
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}
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int __init xics_smp_probe(void)
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{
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/* Setup cause_ipi callback based on which ICP is used */
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smp_ops->cause_ipi = icp_ops->cause_ipi;
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/* Register all the IPIs */
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xics_request_ipi();
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return cpumask_weight(cpu_possible_mask);
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}
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#endif /* CONFIG_SMP */
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void xics_teardown_cpu(void)
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{
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struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
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/*
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* we have to reset the cppr index to 0 because we're
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* not going to return from the IPI
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*/
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os_cppr->index = 0;
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icp_ops->set_priority(0);
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icp_ops->teardown_cpu();
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}
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void xics_kexec_teardown_cpu(int secondary)
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{
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xics_teardown_cpu();
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icp_ops->flush_ipi();
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/*
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* Some machines need to have at least one cpu in the GIQ,
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* so leave the master cpu in the group.
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*/
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if (secondary)
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xics_set_cpu_giq(xics_default_distrib_server, 0);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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/* Interrupts are disabled. */
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void xics_migrate_irqs_away(void)
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{
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int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
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unsigned int irq, virq;
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struct irq_desc *desc;
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/* If we used to be the default server, move to the new "boot_cpuid" */
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if (hw_cpu == xics_default_server)
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xics_update_irq_servers();
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/* Reject any interrupt that was queued to us... */
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icp_ops->set_priority(0);
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/* Remove ourselves from the global interrupt queue */
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xics_set_cpu_giq(xics_default_distrib_server, 0);
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/* Allow IPIs again... */
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icp_ops->set_priority(DEFAULT_PRIORITY);
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for_each_irq_desc(virq, desc) {
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struct irq_chip *chip;
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long server;
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unsigned long flags;
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struct ics *ics;
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/* We can't set affinity on ISA interrupts */
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if (virq < NUM_ISA_INTERRUPTS)
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continue;
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/* We only need to migrate enabled IRQS */
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if (!desc->action)
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continue;
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if (desc->irq_data.domain != xics_host)
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continue;
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irq = desc->irq_data.hwirq;
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/* We need to get IPIs still. */
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if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
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continue;
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chip = irq_desc_get_chip(desc);
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if (!chip || !chip->irq_set_affinity)
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continue;
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raw_spin_lock_irqsave(&desc->lock, flags);
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/* Locate interrupt server */
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server = -1;
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ics = irq_get_chip_data(virq);
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if (ics)
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server = ics->get_server(ics, irq);
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if (server < 0) {
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printk(KERN_ERR "%s: Can't find server for irq %d\n",
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__func__, irq);
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goto unlock;
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}
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/* We only support delivery to all cpus or to one cpu.
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* The irq has to be migrated only in the single cpu
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* case.
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*/
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if (server != hw_cpu)
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goto unlock;
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/* This is expected during cpu offline. */
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if (cpu_online(cpu))
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pr_warning("IRQ %u affinity broken off cpu %u\n",
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virq, cpu);
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/* Reset affinity to all cpus */
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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irq_set_affinity(virq, cpu_all_mask);
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continue;
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unlock:
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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#ifdef CONFIG_SMP
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/*
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* For the moment we only implement delivery to all cpus or one cpu.
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*
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* If the requested affinity is cpu_all_mask, we set global affinity.
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* If not we set it to the first cpu in the mask, even if multiple cpus
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* are set. This is so things like irqbalance (which set core and package
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* wide affinities) do the right thing.
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*
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* We need to fix this to implement support for the links
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*/
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int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
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unsigned int strict_check)
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{
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if (!distribute_irqs)
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return xics_default_server;
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if (!cpumask_subset(cpu_possible_mask, cpumask)) {
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int server = cpumask_first_and(cpu_online_mask, cpumask);
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if (server < nr_cpu_ids)
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return get_hard_smp_processor_id(server);
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if (strict_check)
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return -1;
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}
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/*
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* Workaround issue with some versions of JS20 firmware that
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* deliver interrupts to cpus which haven't been started. This
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* happens when using the maxcpus= boot option.
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*/
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if (cpumask_equal(cpu_online_mask, cpu_present_mask))
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return xics_default_distrib_server;
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return xics_default_server;
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}
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#endif /* CONFIG_SMP */
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static int xics_host_match(struct irq_domain *h, struct device_node *node)
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{
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struct ics *ics;
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list_for_each_entry(ics, &ics_list, link)
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if (ics->host_match(ics, node))
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return 1;
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return 0;
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}
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/* Dummies */
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static void xics_ipi_unmask(struct irq_data *d) { }
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static void xics_ipi_mask(struct irq_data *d) { }
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static struct irq_chip xics_ipi_chip = {
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.name = "XICS",
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.irq_eoi = NULL, /* Patched at init time */
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.irq_mask = xics_ipi_mask,
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.irq_unmask = xics_ipi_unmask,
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};
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static int xics_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct ics *ics;
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pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
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/* They aren't all level sensitive but we just don't really know */
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irq_set_status_flags(virq, IRQ_LEVEL);
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/* Don't call into ICS for IPIs */
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if (hw == XICS_IPI) {
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irq_set_chip_and_handler(virq, &xics_ipi_chip,
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handle_percpu_irq);
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return 0;
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}
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/* Let the ICS setup the chip data */
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list_for_each_entry(ics, &ics_list, link)
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if (ics->map(ics, virq) == 0)
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return 0;
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return -EINVAL;
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}
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static int xics_host_xlate(struct irq_domain *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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/* Current xics implementation translates everything
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* to level. It is not technically right for MSIs but this
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* is irrelevant at this point. We might get smarter in the future
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*/
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*out_hwirq = intspec[0];
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*out_flags = IRQ_TYPE_LEVEL_LOW;
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return 0;
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}
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static struct irq_domain_ops xics_host_ops = {
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.match = xics_host_match,
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.map = xics_host_map,
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.xlate = xics_host_xlate,
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};
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static void __init xics_init_host(void)
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{
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xics_host = irq_domain_add_tree(NULL, &xics_host_ops, NULL);
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BUG_ON(xics_host == NULL);
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irq_set_default_host(xics_host);
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}
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void __init xics_register_ics(struct ics *ics)
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{
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list_add(&ics->link, &ics_list);
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}
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static void __init xics_get_server_size(void)
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{
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struct device_node *np;
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const __be32 *isize;
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/* We fetch the interrupt server size from the first ICS node
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* we find if any
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*/
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np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics");
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if (!np)
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return;
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isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
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if (!isize)
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return;
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xics_interrupt_server_size = be32_to_cpu(*isize);
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of_node_put(np);
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}
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void __init xics_init(void)
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{
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int rc = -1;
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/* Fist locate ICP */
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if (firmware_has_feature(FW_FEATURE_LPAR))
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rc = icp_hv_init();
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if (rc < 0)
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rc = icp_native_init();
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if (rc < 0) {
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pr_warning("XICS: Cannot find a Presentation Controller !\n");
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return;
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}
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/* Copy get_irq callback over to ppc_md */
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ppc_md.get_irq = icp_ops->get_irq;
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/* Patch up IPI chip EOI */
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xics_ipi_chip.irq_eoi = icp_ops->eoi;
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/* Now locate ICS */
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rc = ics_rtas_init();
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if (rc < 0)
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rc = ics_opal_init();
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if (rc < 0)
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pr_warning("XICS: Cannot find a Source Controller !\n");
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/* Initialize common bits */
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xics_get_server_size();
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xics_update_irq_servers();
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xics_init_host();
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xics_setup_cpu();
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}
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