mirror of https://gitee.com/openkylin/linux.git
359 lines
8.9 KiB
C
359 lines
8.9 KiB
C
/*
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Broadcom BCM43xx wireless driver
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Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
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Stefano Brivio <st3@riseup.net>
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Michael Buesch <mbuesch@freenet.de>
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Danny van Dyk <kugelfang@gentoo.org>
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Andreas Jaggi <andreas.jaggi@waterwave.ch>
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Some parts of the code in this file are derived from the ipw2200
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driver Copyright(c) 2003 - 2004 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
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Boston, MA 02110-1301, USA.
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*/
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#include <linux/delay.h>
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#include "bcm43xx.h"
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#include "bcm43xx_power.h"
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#include "bcm43xx_main.h"
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/* Get max/min slowclock frequency
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* as described in http://bcm-specs.sipsolutions.net/PowerControl
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*/
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static int bcm43xx_pctl_clockfreqlimit(struct bcm43xx_private *bcm,
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int get_max)
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{
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int limit = 0;
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int divisor;
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int selection;
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int err;
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u32 tmp;
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struct bcm43xx_coreinfo *old_core;
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if (!(bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL))
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goto out;
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old_core = bcm->current_core;
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err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
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if (err)
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goto out;
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if (bcm->current_core->rev < 6) {
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if ((bcm->bustype == BCM43xx_BUSTYPE_PCMCIA) ||
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(bcm->bustype == BCM43xx_BUSTYPE_SB)) {
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selection = 1;
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divisor = 32;
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} else {
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err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCTL_OUT, &tmp);
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if (err) {
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printk(KERN_ERR PFX "clockfreqlimit pcicfg read failure\n");
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goto out_switchback;
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}
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if (tmp & 0x10) {
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/* PCI */
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selection = 2;
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divisor = 64;
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} else {
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/* XTAL */
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selection = 1;
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divisor = 32;
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}
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}
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} else if (bcm->current_core->rev < 10) {
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selection = (tmp & 0x07);
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if (selection) {
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tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL);
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divisor = 4 * (1 + ((tmp & 0xFFFF0000) >> 16));
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} else
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divisor = 1;
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} else {
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tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SYSCLKCTL);
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divisor = 4 * (1 + ((tmp & 0xFFFF0000) >> 16));
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selection = 1;
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}
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switch (selection) {
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case 0:
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/* LPO */
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if (get_max)
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limit = 43000;
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else
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limit = 25000;
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break;
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case 1:
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/* XTAL */
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if (get_max)
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limit = 20200000;
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else
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limit = 19800000;
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break;
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case 2:
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/* PCI */
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if (get_max)
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limit = 34000000;
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else
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limit = 25000000;
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break;
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default:
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assert(0);
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}
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limit /= divisor;
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out_switchback:
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err = bcm43xx_switch_core(bcm, old_core);
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assert(err == 0);
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out:
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return limit;
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}
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/* init power control
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* as described in http://bcm-specs.sipsolutions.net/PowerControl
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*/
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int bcm43xx_pctl_init(struct bcm43xx_private *bcm)
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{
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int err, maxfreq;
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struct bcm43xx_coreinfo *old_core;
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if (!(bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL))
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return 0;
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old_core = bcm->current_core;
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err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
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if (err == -ENODEV)
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return 0;
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if (err)
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goto out;
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maxfreq = bcm43xx_pctl_clockfreqlimit(bcm, 1);
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY,
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(maxfreq * 150 + 999999) / 1000000);
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_FREFSELDELAY,
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(maxfreq * 15 + 999999) / 1000000);
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err = bcm43xx_switch_core(bcm, old_core);
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assert(err == 0);
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out:
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return err;
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}
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u16 bcm43xx_pctl_powerup_delay(struct bcm43xx_private *bcm)
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{
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u16 delay = 0;
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int err;
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u32 pll_on_delay;
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struct bcm43xx_coreinfo *old_core;
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int minfreq;
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if (bcm->bustype != BCM43xx_BUSTYPE_PCI)
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goto out;
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if (!(bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL))
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goto out;
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old_core = bcm->current_core;
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err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
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if (err == -ENODEV)
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goto out;
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minfreq = bcm43xx_pctl_clockfreqlimit(bcm, 0);
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pll_on_delay = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY);
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delay = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
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err = bcm43xx_switch_core(bcm, old_core);
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assert(err == 0);
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out:
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return delay;
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}
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/* set the powercontrol clock
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* as described in http://bcm-specs.sipsolutions.net/PowerControl
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*/
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int bcm43xx_pctl_set_clock(struct bcm43xx_private *bcm, u16 mode)
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{
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int err;
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struct bcm43xx_coreinfo *old_core;
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u32 tmp;
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old_core = bcm->current_core;
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err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
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if (err == -ENODEV)
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return 0;
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if (err)
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goto out;
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if (bcm->core_chipcommon.rev < 6) {
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if (mode == BCM43xx_PCTL_CLK_FAST) {
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err = bcm43xx_pctl_set_crystal(bcm, 1);
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if (err)
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goto out;
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}
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} else {
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if ((bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL) &&
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(bcm->core_chipcommon.rev < 10)) {
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switch (mode) {
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case BCM43xx_PCTL_CLK_FAST:
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tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL);
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tmp = (tmp & ~BCM43xx_PCTL_FORCE_SLOW) | BCM43xx_PCTL_FORCE_PLL;
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL, tmp);
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break;
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case BCM43xx_PCTL_CLK_SLOW:
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tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL);
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tmp |= BCM43xx_PCTL_FORCE_SLOW;
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL, tmp);
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break;
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case BCM43xx_PCTL_CLK_DYNAMIC:
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tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL);
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tmp &= ~BCM43xx_PCTL_FORCE_SLOW;
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tmp |= BCM43xx_PCTL_FORCE_PLL;
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tmp &= ~BCM43xx_PCTL_DYN_XTAL;
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL, tmp);
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}
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}
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}
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err = bcm43xx_switch_core(bcm, old_core);
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assert(err == 0);
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out:
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return err;
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}
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int bcm43xx_pctl_set_crystal(struct bcm43xx_private *bcm, int on)
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{
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int err;
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u32 in, out, outenable;
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err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCTL_IN, &in);
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if (err)
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goto err_pci;
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err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCTL_OUT, &out);
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if (err)
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goto err_pci;
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err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCTL_OUTENABLE, &outenable);
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if (err)
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goto err_pci;
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outenable |= (BCM43xx_PCTL_XTAL_POWERUP | BCM43xx_PCTL_PLL_POWERDOWN);
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if (on) {
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if (in & 0x40)
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return 0;
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out |= (BCM43xx_PCTL_XTAL_POWERUP | BCM43xx_PCTL_PLL_POWERDOWN);
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err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCTL_OUT, out);
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if (err)
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goto err_pci;
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err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCTL_OUTENABLE, outenable);
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if (err)
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goto err_pci;
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udelay(1000);
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out &= ~BCM43xx_PCTL_PLL_POWERDOWN;
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err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCTL_OUT, out);
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if (err)
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goto err_pci;
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udelay(5000);
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} else {
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if (bcm->current_core->rev < 5)
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return 0;
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if (bcm->sprom.boardflags & BCM43xx_BFL_XTAL_NOSLOW)
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return 0;
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/* XXX: Why BCM43xx_MMIO_RADIO_HWENABLED_xx can't be read at this time?
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* err = bcm43xx_switch_core(bcm, bcm->active_80211_core);
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* if (err)
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* return err;
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* if (((bcm->current_core->rev >= 3) &&
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* (bcm43xx_read32(bcm, BCM43xx_MMIO_RADIO_HWENABLED_HI) & (1 << 16))) ||
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* ((bcm->current_core->rev < 3) &&
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* !(bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_HWENABLED_LO) & (1 << 4))))
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* return 0;
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* err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
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* if (err)
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* return err;
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*/
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err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
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if (err)
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goto out;
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out &= ~BCM43xx_PCTL_XTAL_POWERUP;
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out |= BCM43xx_PCTL_PLL_POWERDOWN;
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err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCTL_OUT, out);
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if (err)
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goto err_pci;
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err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCTL_OUTENABLE, outenable);
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if (err)
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goto err_pci;
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}
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out:
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return err;
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err_pci:
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printk(KERN_ERR PFX "Error: pctl_set_clock() could not access PCI config space!\n");
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err = -EBUSY;
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goto out;
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}
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/* Set the PowerSavingControlBits.
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* Bitvalues:
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* 0 => unset the bit
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* 1 => set the bit
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* -1 => calculate the bit
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*/
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void bcm43xx_power_saving_ctl_bits(struct bcm43xx_private *bcm,
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int bit25, int bit26)
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{
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int i;
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u32 status;
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//FIXME: Force 25 to off and 26 to on for now:
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bit25 = 0;
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bit26 = 1;
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if (bit25 == -1) {
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//TODO: If powersave is not off and FIXME is not set and we are not in adhoc
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// and thus is not an AP and we are associated, set bit 25
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}
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if (bit26 == -1) {
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//TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
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// or we are associated, or FIXME, or the latest PS-Poll packet sent was
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// successful, set bit26
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}
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status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
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if (bit25)
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status |= BCM43xx_SBF_PS1;
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else
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status &= ~BCM43xx_SBF_PS1;
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if (bit26)
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status |= BCM43xx_SBF_PS2;
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else
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status &= ~BCM43xx_SBF_PS2;
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bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
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if (bit26 && bcm->current_core->rev >= 5) {
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for (i = 0; i < 100; i++) {
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if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0040) != 4)
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break;
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udelay(10);
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}
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}
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}
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