mirror of https://gitee.com/openkylin/linux.git
374 lines
12 KiB
C
374 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/soc/mediatek/mtk-mmsys.h>
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#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
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#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
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#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
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#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
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#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
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#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
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#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
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#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
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#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
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#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
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#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
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#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
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#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
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#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
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#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
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#define DISP_REG_CONFIG_OUT_SEL 0x04c
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#define DISP_REG_CONFIG_DSI_SEL 0x050
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#define DISP_REG_CONFIG_DPI_SEL 0x064
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#define OVL0_MOUT_EN_COLOR0 0x1
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#define OD_MOUT_EN_RDMA0 0x1
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#define OD1_MOUT_EN_RDMA1 BIT(16)
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#define UFOE_MOUT_EN_DSI0 0x1
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#define COLOR0_SEL_IN_OVL0 0x1
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#define OVL1_MOUT_EN_COLOR1 0x1
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#define GAMMA_MOUT_EN_RDMA1 0x1
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#define RDMA0_SOUT_DPI0 0x2
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#define RDMA0_SOUT_DPI1 0x3
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#define RDMA0_SOUT_DSI1 0x1
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#define RDMA0_SOUT_DSI2 0x4
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#define RDMA0_SOUT_DSI3 0x5
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#define RDMA1_SOUT_DPI0 0x2
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#define RDMA1_SOUT_DPI1 0x3
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#define RDMA1_SOUT_DSI1 0x1
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#define RDMA1_SOUT_DSI2 0x4
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#define RDMA1_SOUT_DSI3 0x5
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#define RDMA2_SOUT_DPI0 0x2
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#define RDMA2_SOUT_DPI1 0x3
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#define RDMA2_SOUT_DSI1 0x1
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#define RDMA2_SOUT_DSI2 0x4
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#define RDMA2_SOUT_DSI3 0x5
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#define DPI0_SEL_IN_RDMA1 0x1
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#define DPI0_SEL_IN_RDMA2 0x3
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#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
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#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
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#define DSI0_SEL_IN_RDMA1 0x1
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#define DSI0_SEL_IN_RDMA2 0x4
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#define DSI1_SEL_IN_RDMA1 0x1
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#define DSI1_SEL_IN_RDMA2 0x4
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#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
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#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
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#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
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#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
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#define COLOR1_SEL_IN_OVL1 0x1
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#define OVL_MOUT_EN_RDMA 0x1
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#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
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#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
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#define DSI_SEL_IN_BLS 0x0
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#define DPI_SEL_IN_BLS 0x0
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#define DSI_SEL_IN_RDMA 0x1
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struct mtk_mmsys_driver_data {
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const char *clk_driver;
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};
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static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
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.clk_driver = "clk-mt2701-mm",
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};
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static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
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.clk_driver = "clk-mt2712-mm",
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};
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static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
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.clk_driver = "clk-mt6779-mm",
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};
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static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
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.clk_driver = "clk-mt6797-mm",
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};
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static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
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.clk_driver = "clk-mt8173-mm",
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};
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static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
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.clk_driver = "clk-mt8183-mm",
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};
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static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next,
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unsigned int *addr)
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{
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unsigned int value;
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if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
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*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
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value = OVL0_MOUT_EN_COLOR0;
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} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
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*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
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value = OVL_MOUT_EN_RDMA;
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} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
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*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
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value = OD_MOUT_EN_RDMA0;
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} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
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*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
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value = UFOE_MOUT_EN_DSI0;
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} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
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*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
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value = OVL1_MOUT_EN_COLOR1;
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} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
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*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
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value = GAMMA_MOUT_EN_RDMA1;
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} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
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*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
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value = OD1_MOUT_EN_RDMA1;
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} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
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*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
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value = RDMA0_SOUT_DPI0;
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} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
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*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
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value = RDMA0_SOUT_DPI1;
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} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
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*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
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value = RDMA0_SOUT_DSI1;
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} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
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*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
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value = RDMA0_SOUT_DSI2;
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} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
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*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
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value = RDMA0_SOUT_DSI3;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
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*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
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value = RDMA1_SOUT_DSI1;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
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*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
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value = RDMA1_SOUT_DSI2;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
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*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
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value = RDMA1_SOUT_DSI3;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
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*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
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value = RDMA1_SOUT_DPI0;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
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*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
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value = RDMA1_SOUT_DPI1;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
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*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
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value = RDMA2_SOUT_DPI0;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
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*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
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value = RDMA2_SOUT_DPI1;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
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*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
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value = RDMA2_SOUT_DSI1;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
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*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
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value = RDMA2_SOUT_DSI2;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
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*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
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value = RDMA2_SOUT_DSI3;
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} else {
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value = 0;
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}
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return value;
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}
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static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next,
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unsigned int *addr)
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{
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unsigned int value;
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if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
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*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
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value = COLOR0_SEL_IN_OVL0;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
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*addr = DISP_REG_CONFIG_DPI_SEL_IN;
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value = DPI0_SEL_IN_RDMA1;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
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*addr = DISP_REG_CONFIG_DPI_SEL_IN;
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value = DPI1_SEL_IN_RDMA1;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
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*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
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value = DSI0_SEL_IN_RDMA1;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
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*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
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value = DSI1_SEL_IN_RDMA1;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
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*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
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value = DSI2_SEL_IN_RDMA1;
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} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
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*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
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value = DSI3_SEL_IN_RDMA1;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
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*addr = DISP_REG_CONFIG_DPI_SEL_IN;
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value = DPI0_SEL_IN_RDMA2;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
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*addr = DISP_REG_CONFIG_DPI_SEL_IN;
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value = DPI1_SEL_IN_RDMA2;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
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*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
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value = DSI0_SEL_IN_RDMA2;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
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*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
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value = DSI1_SEL_IN_RDMA2;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
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*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
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value = DSI2_SEL_IN_RDMA2;
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} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
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*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
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value = DSI3_SEL_IN_RDMA2;
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} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
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*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
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value = COLOR1_SEL_IN_OVL1;
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} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
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*addr = DISP_REG_CONFIG_DSI_SEL;
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value = DSI_SEL_IN_BLS;
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} else {
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value = 0;
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}
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return value;
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}
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static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next)
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{
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if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
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writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
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config_regs + DISP_REG_CONFIG_OUT_SEL);
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} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
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writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
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config_regs + DISP_REG_CONFIG_OUT_SEL);
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writel_relaxed(DSI_SEL_IN_RDMA,
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config_regs + DISP_REG_CONFIG_DSI_SEL);
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writel_relaxed(DPI_SEL_IN_BLS,
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config_regs + DISP_REG_CONFIG_DPI_SEL);
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}
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}
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void mtk_mmsys_ddp_connect(struct device *dev,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next)
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{
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void __iomem *config_regs = dev_get_drvdata(dev);
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unsigned int addr, value, reg;
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value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
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if (value) {
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reg = readl_relaxed(config_regs + addr) | value;
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writel_relaxed(reg, config_regs + addr);
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}
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mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
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value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
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if (value) {
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reg = readl_relaxed(config_regs + addr) | value;
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writel_relaxed(reg, config_regs + addr);
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}
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
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void mtk_mmsys_ddp_disconnect(struct device *dev,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next)
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{
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void __iomem *config_regs = dev_get_drvdata(dev);
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unsigned int addr, value, reg;
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value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
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if (value) {
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reg = readl_relaxed(config_regs + addr) & ~value;
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writel_relaxed(reg, config_regs + addr);
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}
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value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
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if (value) {
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reg = readl_relaxed(config_regs + addr) & ~value;
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writel_relaxed(reg, config_regs + addr);
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}
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
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static int mtk_mmsys_probe(struct platform_device *pdev)
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{
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const struct mtk_mmsys_driver_data *data;
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struct device *dev = &pdev->dev;
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struct platform_device *clks;
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struct platform_device *drm;
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void __iomem *config_regs;
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int ret;
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config_regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(config_regs)) {
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ret = PTR_ERR(config_regs);
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dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, config_regs);
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data = of_device_get_match_data(&pdev->dev);
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clks = platform_device_register_data(&pdev->dev, data->clk_driver,
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PLATFORM_DEVID_AUTO, NULL, 0);
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if (IS_ERR(clks))
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return PTR_ERR(clks);
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drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
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PLATFORM_DEVID_AUTO, NULL, 0);
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if (IS_ERR(drm)) {
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platform_device_unregister(clks);
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return PTR_ERR(drm);
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}
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return 0;
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}
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static const struct of_device_id of_match_mtk_mmsys[] = {
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{
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.compatible = "mediatek,mt2701-mmsys",
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.data = &mt2701_mmsys_driver_data,
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},
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{
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.compatible = "mediatek,mt2712-mmsys",
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.data = &mt2712_mmsys_driver_data,
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},
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{
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.compatible = "mediatek,mt6779-mmsys",
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.data = &mt6779_mmsys_driver_data,
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},
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{
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.compatible = "mediatek,mt6797-mmsys",
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.data = &mt6797_mmsys_driver_data,
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},
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{
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.compatible = "mediatek,mt8173-mmsys",
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.data = &mt8173_mmsys_driver_data,
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},
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{
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.compatible = "mediatek,mt8183-mmsys",
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.data = &mt8183_mmsys_driver_data,
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},
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{ }
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};
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static struct platform_driver mtk_mmsys_drv = {
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.driver = {
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.name = "mtk-mmsys",
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.of_match_table = of_match_mtk_mmsys,
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},
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.probe = mtk_mmsys_probe,
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};
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builtin_platform_driver(mtk_mmsys_drv);
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