mirror of https://gitee.com/openkylin/linux.git
630 lines
15 KiB
C
630 lines
15 KiB
C
/*
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* nvme-lightnvm.c - LightNVM NVMe device
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*
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* Copyright (C) 2014-2015 IT University of Copenhagen
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* Initial release: Matias Bjorling <mb@lightnvm.io>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
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* USA.
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*
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*/
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#include "nvme.h"
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#include <linux/nvme.h>
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#include <linux/bitops.h>
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#include <linux/lightnvm.h>
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#include <linux/vmalloc.h>
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enum nvme_nvm_admin_opcode {
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nvme_nvm_admin_identity = 0xe2,
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nvme_nvm_admin_get_l2p_tbl = 0xea,
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nvme_nvm_admin_get_bb_tbl = 0xf2,
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nvme_nvm_admin_set_bb_tbl = 0xf1,
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};
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struct nvme_nvm_hb_rw {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd2;
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__le64 metadata;
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__le64 prp1;
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__le64 prp2;
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__le64 spba;
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__le16 length;
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__le16 control;
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__le32 dsmgmt;
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__le64 slba;
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};
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struct nvme_nvm_ph_rw {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd2;
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__le64 metadata;
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__le64 prp1;
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__le64 prp2;
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__le64 spba;
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__le16 length;
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__le16 control;
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__le32 dsmgmt;
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__le64 resv;
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};
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struct nvme_nvm_identity {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd[2];
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__le64 prp1;
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__le64 prp2;
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__le32 chnl_off;
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__u32 rsvd11[5];
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};
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struct nvme_nvm_l2ptbl {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__le32 cdw2[4];
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__le64 prp1;
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__le64 prp2;
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__le64 slba;
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__le32 nlb;
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__le16 cdw14[6];
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};
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struct nvme_nvm_getbbtbl {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd[2];
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__le64 prp1;
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__le64 prp2;
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__le64 spba;
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__u32 rsvd4[4];
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};
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struct nvme_nvm_setbbtbl {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__le64 rsvd[2];
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__le64 prp1;
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__le64 prp2;
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__le64 spba;
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__le16 nlb;
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__u8 value;
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__u8 rsvd3;
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__u32 rsvd4[3];
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};
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struct nvme_nvm_erase_blk {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd[2];
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__le64 prp1;
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__le64 prp2;
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__le64 spba;
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__le16 length;
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__le16 control;
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__le32 dsmgmt;
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__le64 resv;
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};
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struct nvme_nvm_command {
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union {
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struct nvme_common_command common;
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struct nvme_nvm_identity identity;
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struct nvme_nvm_hb_rw hb_rw;
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struct nvme_nvm_ph_rw ph_rw;
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struct nvme_nvm_l2ptbl l2p;
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struct nvme_nvm_getbbtbl get_bb;
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struct nvme_nvm_setbbtbl set_bb;
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struct nvme_nvm_erase_blk erase;
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};
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};
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struct nvme_nvm_completion {
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__le64 result; /* Used by LightNVM to return ppa completions */
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__le16 sq_head; /* how much of this queue may be reclaimed */
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__le16 sq_id; /* submission queue that generated this entry */
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__u16 command_id; /* of the command which completed */
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__le16 status; /* did the command fail, and if so, why? */
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};
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#define NVME_NVM_LP_MLC_PAIRS 886
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struct nvme_nvm_lp_mlc {
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__u16 num_pairs;
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__u8 pairs[NVME_NVM_LP_MLC_PAIRS];
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};
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struct nvme_nvm_lp_tbl {
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__u8 id[8];
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struct nvme_nvm_lp_mlc mlc;
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};
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struct nvme_nvm_id_group {
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__u8 mtype;
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__u8 fmtype;
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__le16 res16;
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__u8 num_ch;
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__u8 num_lun;
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__u8 num_pln;
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__u8 rsvd1;
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__le16 num_blk;
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__le16 num_pg;
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__le16 fpg_sz;
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__le16 csecs;
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__le16 sos;
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__le16 rsvd2;
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__le32 trdt;
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__le32 trdm;
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__le32 tprt;
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__le32 tprm;
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__le32 tbet;
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__le32 tbem;
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__le32 mpos;
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__le32 mccap;
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__le16 cpar;
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__u8 reserved[10];
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struct nvme_nvm_lp_tbl lptbl;
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} __packed;
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struct nvme_nvm_addr_format {
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__u8 ch_offset;
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__u8 ch_len;
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__u8 lun_offset;
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__u8 lun_len;
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__u8 pln_offset;
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__u8 pln_len;
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__u8 blk_offset;
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__u8 blk_len;
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__u8 pg_offset;
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__u8 pg_len;
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__u8 sect_offset;
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__u8 sect_len;
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__u8 res[4];
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} __packed;
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struct nvme_nvm_id {
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__u8 ver_id;
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__u8 vmnt;
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__u8 cgrps;
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__u8 res;
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__le32 cap;
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__le32 dom;
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struct nvme_nvm_addr_format ppaf;
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__u8 resv[228];
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struct nvme_nvm_id_group groups[4];
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} __packed;
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struct nvme_nvm_bb_tbl {
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__u8 tblid[4];
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__le16 verid;
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__le16 revid;
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__le32 rvsd1;
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__le32 tblks;
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__le32 tfact;
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__le32 tgrown;
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__le32 tdresv;
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__le32 thresv;
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__le32 rsvd2[8];
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__u8 blk[0];
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};
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/*
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* Check we didn't inadvertently grow the command struct
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*/
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static inline void _nvme_nvm_check_size(void)
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{
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BUILD_BUG_ON(sizeof(struct nvme_nvm_identity) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_nvm_hb_rw) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_nvm_ph_rw) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_nvm_getbbtbl) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_nvm_setbbtbl) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_nvm_l2ptbl) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_nvm_erase_blk) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_nvm_id_group) != 960);
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BUILD_BUG_ON(sizeof(struct nvme_nvm_addr_format) != 128);
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BUILD_BUG_ON(sizeof(struct nvme_nvm_id) != 4096);
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BUILD_BUG_ON(sizeof(struct nvme_nvm_bb_tbl) != 512);
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}
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static int init_grps(struct nvm_id *nvm_id, struct nvme_nvm_id *nvme_nvm_id)
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{
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struct nvme_nvm_id_group *src;
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struct nvm_id_group *dst;
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int i, end;
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end = min_t(u32, 4, nvm_id->cgrps);
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for (i = 0; i < end; i++) {
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src = &nvme_nvm_id->groups[i];
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dst = &nvm_id->groups[i];
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dst->mtype = src->mtype;
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dst->fmtype = src->fmtype;
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dst->num_ch = src->num_ch;
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dst->num_lun = src->num_lun;
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dst->num_pln = src->num_pln;
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dst->num_pg = le16_to_cpu(src->num_pg);
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dst->num_blk = le16_to_cpu(src->num_blk);
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dst->fpg_sz = le16_to_cpu(src->fpg_sz);
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dst->csecs = le16_to_cpu(src->csecs);
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dst->sos = le16_to_cpu(src->sos);
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dst->trdt = le32_to_cpu(src->trdt);
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dst->trdm = le32_to_cpu(src->trdm);
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dst->tprt = le32_to_cpu(src->tprt);
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dst->tprm = le32_to_cpu(src->tprm);
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dst->tbet = le32_to_cpu(src->tbet);
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dst->tbem = le32_to_cpu(src->tbem);
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dst->mpos = le32_to_cpu(src->mpos);
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dst->mccap = le32_to_cpu(src->mccap);
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dst->cpar = le16_to_cpu(src->cpar);
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if (dst->fmtype == NVM_ID_FMTYPE_MLC) {
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memcpy(dst->lptbl.id, src->lptbl.id, 8);
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dst->lptbl.mlc.num_pairs =
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le16_to_cpu(src->lptbl.mlc.num_pairs);
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if (dst->lptbl.mlc.num_pairs > NVME_NVM_LP_MLC_PAIRS) {
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pr_err("nvm: number of MLC pairs not supported\n");
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return -EINVAL;
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}
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memcpy(dst->lptbl.mlc.pairs, src->lptbl.mlc.pairs,
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dst->lptbl.mlc.num_pairs);
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}
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}
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return 0;
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}
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static int nvme_nvm_identity(struct nvm_dev *nvmdev, struct nvm_id *nvm_id)
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{
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struct nvme_ns *ns = nvmdev->q->queuedata;
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struct nvme_nvm_id *nvme_nvm_id;
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struct nvme_nvm_command c = {};
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int ret;
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c.identity.opcode = nvme_nvm_admin_identity;
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c.identity.nsid = cpu_to_le32(ns->ns_id);
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c.identity.chnl_off = 0;
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nvme_nvm_id = kmalloc(sizeof(struct nvme_nvm_id), GFP_KERNEL);
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if (!nvme_nvm_id)
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return -ENOMEM;
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ret = nvme_submit_sync_cmd(ns->ctrl->admin_q, (struct nvme_command *)&c,
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nvme_nvm_id, sizeof(struct nvme_nvm_id));
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if (ret) {
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ret = -EIO;
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goto out;
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}
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nvm_id->ver_id = nvme_nvm_id->ver_id;
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nvm_id->vmnt = nvme_nvm_id->vmnt;
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nvm_id->cgrps = nvme_nvm_id->cgrps;
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nvm_id->cap = le32_to_cpu(nvme_nvm_id->cap);
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nvm_id->dom = le32_to_cpu(nvme_nvm_id->dom);
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memcpy(&nvm_id->ppaf, &nvme_nvm_id->ppaf,
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sizeof(struct nvme_nvm_addr_format));
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ret = init_grps(nvm_id, nvme_nvm_id);
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out:
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kfree(nvme_nvm_id);
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return ret;
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}
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static int nvme_nvm_get_l2p_tbl(struct nvm_dev *nvmdev, u64 slba, u32 nlb,
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nvm_l2p_update_fn *update_l2p, void *priv)
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{
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struct nvme_ns *ns = nvmdev->q->queuedata;
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struct nvme_nvm_command c = {};
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u32 len = queue_max_hw_sectors(ns->ctrl->admin_q) << 9;
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u32 nlb_pr_rq = len / sizeof(u64);
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u64 cmd_slba = slba;
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void *entries;
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int ret = 0;
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c.l2p.opcode = nvme_nvm_admin_get_l2p_tbl;
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c.l2p.nsid = cpu_to_le32(ns->ns_id);
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entries = kmalloc(len, GFP_KERNEL);
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if (!entries)
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return -ENOMEM;
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while (nlb) {
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u32 cmd_nlb = min(nlb_pr_rq, nlb);
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c.l2p.slba = cpu_to_le64(cmd_slba);
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c.l2p.nlb = cpu_to_le32(cmd_nlb);
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ret = nvme_submit_sync_cmd(ns->ctrl->admin_q,
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(struct nvme_command *)&c, entries, len);
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if (ret) {
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dev_err(ns->ctrl->device,
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"L2P table transfer failed (%d)\n", ret);
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ret = -EIO;
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goto out;
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}
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if (update_l2p(cmd_slba, cmd_nlb, entries, priv)) {
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ret = -EINTR;
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goto out;
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}
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cmd_slba += cmd_nlb;
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nlb -= cmd_nlb;
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}
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out:
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kfree(entries);
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return ret;
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}
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static int nvme_nvm_get_bb_tbl(struct nvm_dev *nvmdev, struct ppa_addr ppa,
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u8 *blks)
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{
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struct request_queue *q = nvmdev->q;
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struct nvme_ns *ns = q->queuedata;
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struct nvme_ctrl *ctrl = ns->ctrl;
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struct nvme_nvm_command c = {};
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struct nvme_nvm_bb_tbl *bb_tbl;
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int nr_blks = nvmdev->blks_per_lun * nvmdev->plane_mode;
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int tblsz = sizeof(struct nvme_nvm_bb_tbl) + nr_blks;
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int ret = 0;
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c.get_bb.opcode = nvme_nvm_admin_get_bb_tbl;
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c.get_bb.nsid = cpu_to_le32(ns->ns_id);
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c.get_bb.spba = cpu_to_le64(ppa.ppa);
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bb_tbl = kzalloc(tblsz, GFP_KERNEL);
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if (!bb_tbl)
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return -ENOMEM;
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ret = nvme_submit_sync_cmd(ctrl->admin_q, (struct nvme_command *)&c,
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bb_tbl, tblsz);
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if (ret) {
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dev_err(ctrl->device, "get bad block table failed (%d)\n", ret);
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ret = -EIO;
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goto out;
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}
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if (bb_tbl->tblid[0] != 'B' || bb_tbl->tblid[1] != 'B' ||
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bb_tbl->tblid[2] != 'L' || bb_tbl->tblid[3] != 'T') {
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dev_err(ctrl->device, "bbt format mismatch\n");
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ret = -EINVAL;
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goto out;
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}
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if (le16_to_cpu(bb_tbl->verid) != 1) {
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ret = -EINVAL;
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dev_err(ctrl->device, "bbt version not supported\n");
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goto out;
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}
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if (le32_to_cpu(bb_tbl->tblks) != nr_blks) {
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ret = -EINVAL;
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dev_err(ctrl->device,
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"bbt unsuspected blocks returned (%u!=%u)",
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le32_to_cpu(bb_tbl->tblks), nr_blks);
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goto out;
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}
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memcpy(blks, bb_tbl->blk, nvmdev->blks_per_lun * nvmdev->plane_mode);
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out:
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kfree(bb_tbl);
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return ret;
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}
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static int nvme_nvm_set_bb_tbl(struct nvm_dev *nvmdev, struct ppa_addr *ppas,
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int nr_ppas, int type)
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{
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struct nvme_ns *ns = nvmdev->q->queuedata;
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struct nvme_nvm_command c = {};
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int ret = 0;
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c.set_bb.opcode = nvme_nvm_admin_set_bb_tbl;
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c.set_bb.nsid = cpu_to_le32(ns->ns_id);
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c.set_bb.spba = cpu_to_le64(ppas->ppa);
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c.set_bb.nlb = cpu_to_le16(nr_ppas - 1);
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c.set_bb.value = type;
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ret = nvme_submit_sync_cmd(ns->ctrl->admin_q, (struct nvme_command *)&c,
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NULL, 0);
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if (ret)
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dev_err(ns->ctrl->device, "set bad block table failed (%d)\n",
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ret);
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return ret;
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}
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static inline void nvme_nvm_rqtocmd(struct request *rq, struct nvm_rq *rqd,
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struct nvme_ns *ns, struct nvme_nvm_command *c)
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{
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c->ph_rw.opcode = rqd->opcode;
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c->ph_rw.nsid = cpu_to_le32(ns->ns_id);
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c->ph_rw.spba = cpu_to_le64(rqd->ppa_addr.ppa);
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c->ph_rw.metadata = cpu_to_le64(rqd->dma_meta_list);
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c->ph_rw.control = cpu_to_le16(rqd->flags);
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c->ph_rw.length = cpu_to_le16(rqd->nr_ppas - 1);
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if (rqd->opcode == NVM_OP_HBWRITE || rqd->opcode == NVM_OP_HBREAD)
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c->hb_rw.slba = cpu_to_le64(nvme_block_nr(ns,
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|
rqd->bio->bi_iter.bi_sector));
|
|
}
|
|
|
|
static void nvme_nvm_end_io(struct request *rq, int error)
|
|
{
|
|
struct nvm_rq *rqd = rq->end_io_data;
|
|
struct nvme_nvm_completion *cqe = rq->special;
|
|
|
|
if (cqe)
|
|
rqd->ppa_status = le64_to_cpu(cqe->result);
|
|
|
|
nvm_end_io(rqd, error);
|
|
|
|
kfree(rq->cmd);
|
|
blk_mq_free_request(rq);
|
|
}
|
|
|
|
static int nvme_nvm_submit_io(struct nvm_dev *dev, struct nvm_rq *rqd)
|
|
{
|
|
struct request_queue *q = dev->q;
|
|
struct nvme_ns *ns = q->queuedata;
|
|
struct request *rq;
|
|
struct bio *bio = rqd->bio;
|
|
struct nvme_nvm_command *cmd;
|
|
|
|
rq = blk_mq_alloc_request(q, bio_rw(bio), 0);
|
|
if (IS_ERR(rq))
|
|
return -ENOMEM;
|
|
|
|
cmd = kzalloc(sizeof(struct nvme_nvm_command) +
|
|
sizeof(struct nvme_nvm_completion), GFP_KERNEL);
|
|
if (!cmd) {
|
|
blk_mq_free_request(rq);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
rq->cmd_type = REQ_TYPE_DRV_PRIV;
|
|
rq->ioprio = bio_prio(bio);
|
|
|
|
if (bio_has_data(bio))
|
|
rq->nr_phys_segments = bio_phys_segments(q, bio);
|
|
|
|
rq->__data_len = bio->bi_iter.bi_size;
|
|
rq->bio = rq->biotail = bio;
|
|
|
|
nvme_nvm_rqtocmd(rq, rqd, ns, cmd);
|
|
|
|
rq->cmd = (unsigned char *)cmd;
|
|
rq->cmd_len = sizeof(struct nvme_nvm_command);
|
|
rq->special = cmd + 1;
|
|
|
|
rq->end_io_data = rqd;
|
|
|
|
blk_execute_rq_nowait(q, NULL, rq, 0, nvme_nvm_end_io);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nvme_nvm_erase_block(struct nvm_dev *dev, struct nvm_rq *rqd)
|
|
{
|
|
struct request_queue *q = dev->q;
|
|
struct nvme_ns *ns = q->queuedata;
|
|
struct nvme_nvm_command c = {};
|
|
|
|
c.erase.opcode = NVM_OP_ERASE;
|
|
c.erase.nsid = cpu_to_le32(ns->ns_id);
|
|
c.erase.spba = cpu_to_le64(rqd->ppa_addr.ppa);
|
|
c.erase.length = cpu_to_le16(rqd->nr_ppas - 1);
|
|
|
|
return nvme_submit_sync_cmd(q, (struct nvme_command *)&c, NULL, 0);
|
|
}
|
|
|
|
static void *nvme_nvm_create_dma_pool(struct nvm_dev *nvmdev, char *name)
|
|
{
|
|
struct nvme_ns *ns = nvmdev->q->queuedata;
|
|
|
|
return dma_pool_create(name, ns->ctrl->dev, PAGE_SIZE, PAGE_SIZE, 0);
|
|
}
|
|
|
|
static void nvme_nvm_destroy_dma_pool(void *pool)
|
|
{
|
|
struct dma_pool *dma_pool = pool;
|
|
|
|
dma_pool_destroy(dma_pool);
|
|
}
|
|
|
|
static void *nvme_nvm_dev_dma_alloc(struct nvm_dev *dev, void *pool,
|
|
gfp_t mem_flags, dma_addr_t *dma_handler)
|
|
{
|
|
return dma_pool_alloc(pool, mem_flags, dma_handler);
|
|
}
|
|
|
|
static void nvme_nvm_dev_dma_free(void *pool, void *addr,
|
|
dma_addr_t dma_handler)
|
|
{
|
|
dma_pool_free(pool, addr, dma_handler);
|
|
}
|
|
|
|
static struct nvm_dev_ops nvme_nvm_dev_ops = {
|
|
.identity = nvme_nvm_identity,
|
|
|
|
.get_l2p_tbl = nvme_nvm_get_l2p_tbl,
|
|
|
|
.get_bb_tbl = nvme_nvm_get_bb_tbl,
|
|
.set_bb_tbl = nvme_nvm_set_bb_tbl,
|
|
|
|
.submit_io = nvme_nvm_submit_io,
|
|
.erase_block = nvme_nvm_erase_block,
|
|
|
|
.create_dma_pool = nvme_nvm_create_dma_pool,
|
|
.destroy_dma_pool = nvme_nvm_destroy_dma_pool,
|
|
.dev_dma_alloc = nvme_nvm_dev_dma_alloc,
|
|
.dev_dma_free = nvme_nvm_dev_dma_free,
|
|
|
|
.max_phys_sect = 64,
|
|
};
|
|
|
|
int nvme_nvm_register(struct request_queue *q, char *disk_name)
|
|
{
|
|
return nvm_register(q, disk_name, &nvme_nvm_dev_ops);
|
|
}
|
|
|
|
void nvme_nvm_unregister(struct request_queue *q, char *disk_name)
|
|
{
|
|
nvm_unregister(disk_name);
|
|
}
|
|
|
|
/* move to shared place when used in multiple places. */
|
|
#define PCI_VENDOR_ID_CNEX 0x1d1d
|
|
#define PCI_DEVICE_ID_CNEX_WL 0x2807
|
|
#define PCI_DEVICE_ID_CNEX_QEMU 0x1f1f
|
|
|
|
int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
|
|
{
|
|
struct nvme_ctrl *ctrl = ns->ctrl;
|
|
/* XXX: this is poking into PCI structures from generic code! */
|
|
struct pci_dev *pdev = to_pci_dev(ctrl->dev);
|
|
|
|
/* QEMU NVMe simulator - PCI ID + Vendor specific bit */
|
|
if (pdev->vendor == PCI_VENDOR_ID_CNEX &&
|
|
pdev->device == PCI_DEVICE_ID_CNEX_QEMU &&
|
|
id->vs[0] == 0x1)
|
|
return 1;
|
|
|
|
/* CNEX Labs - PCI ID + Vendor specific bit */
|
|
if (pdev->vendor == PCI_VENDOR_ID_CNEX &&
|
|
pdev->device == PCI_DEVICE_ID_CNEX_WL &&
|
|
id->vs[0] == 0x1)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|