mirror of https://gitee.com/openkylin/linux.git
691 lines
19 KiB
C
691 lines
19 KiB
C
/*
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* Copyright (c) 2014 Marvell Technology Group Ltd.
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*
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Alexandre Belloni <alexandre.belloni@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/berlin2.h>
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#include "berlin2-avpll.h"
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#include "berlin2-div.h"
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#include "berlin2-pll.h"
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#include "common.h"
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#define REG_PINMUX0 0x0000
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#define REG_PINMUX1 0x0004
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#define REG_SYSPLLCTL0 0x0014
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#define REG_SYSPLLCTL4 0x0024
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#define REG_MEMPLLCTL0 0x0028
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#define REG_MEMPLLCTL4 0x0038
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#define REG_CPUPLLCTL0 0x003c
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#define REG_CPUPLLCTL4 0x004c
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#define REG_AVPLLCTL0 0x0050
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#define REG_AVPLLCTL31 0x00cc
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#define REG_AVPLLCTL62 0x0148
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#define REG_PLLSTATUS 0x014c
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#define REG_CLKENABLE 0x0150
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#define REG_CLKSELECT0 0x0154
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#define REG_CLKSELECT1 0x0158
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#define REG_CLKSELECT2 0x015c
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#define REG_CLKSELECT3 0x0160
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#define REG_CLKSWITCH0 0x0164
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#define REG_CLKSWITCH1 0x0168
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#define REG_RESET_TRIGGER 0x0178
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#define REG_RESET_STATUS0 0x017c
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#define REG_RESET_STATUS1 0x0180
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#define REG_SW_GENERIC0 0x0184
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#define REG_SW_GENERIC3 0x0190
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#define REG_PRODUCTID 0x01cc
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#define REG_PRODUCTID_EXT 0x01d0
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#define REG_GFX3DCORE_CLKCTL 0x022c
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#define REG_GFX3DSYS_CLKCTL 0x0230
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#define REG_ARC_CLKCTL 0x0234
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#define REG_VIP_CLKCTL 0x0238
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#define REG_SDIO0XIN_CLKCTL 0x023c
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#define REG_SDIO1XIN_CLKCTL 0x0240
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#define REG_GFX3DEXTRA_CLKCTL 0x0244
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#define REG_GFX3D_RESET 0x0248
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#define REG_GC360_CLKCTL 0x024c
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#define REG_SDIO_DLLMST_CLKCTL 0x0250
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/*
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* BG2/BG2CD SoCs have the following audio/video I/O units:
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*
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* audiohd: HDMI TX audio
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* audio0: 7.1ch TX
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* audio1: 2ch TX
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* audio2: 2ch RX
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* audio3: SPDIF TX
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* video0: HDMI video
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* video1: Secondary video
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* video2: SD auxiliary video
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*
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* There are no external audio clocks (ACLKI0, ACLKI1) and
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* only one external video clock (VCLKI0).
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*
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* Currently missing bits and pieces:
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* - audio_fast_pll is unknown
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* - audiohd_pll is unknown
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* - video0_pll is unknown
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* - audio[023], audiohd parent pll is assumed to be audio_fast_pll
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*
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*/
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#define MAX_CLKS 41
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static struct clk *clks[MAX_CLKS];
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static struct clk_onecell_data clk_data;
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static DEFINE_SPINLOCK(lock);
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static void __iomem *gbase;
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enum {
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REFCLK, VIDEO_EXT0,
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SYSPLL, MEMPLL, CPUPLL,
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AVPLL_A1, AVPLL_A2, AVPLL_A3, AVPLL_A4,
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AVPLL_A5, AVPLL_A6, AVPLL_A7, AVPLL_A8,
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AVPLL_B1, AVPLL_B2, AVPLL_B3, AVPLL_B4,
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AVPLL_B5, AVPLL_B6, AVPLL_B7, AVPLL_B8,
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AUDIO1_PLL, AUDIO_FAST_PLL,
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VIDEO0_PLL, VIDEO0_IN,
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VIDEO1_PLL, VIDEO1_IN,
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VIDEO2_PLL, VIDEO2_IN,
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};
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static const char *clk_names[] = {
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[REFCLK] = "refclk",
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[VIDEO_EXT0] = "video_ext0",
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[SYSPLL] = "syspll",
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[MEMPLL] = "mempll",
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[CPUPLL] = "cpupll",
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[AVPLL_A1] = "avpll_a1",
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[AVPLL_A2] = "avpll_a2",
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[AVPLL_A3] = "avpll_a3",
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[AVPLL_A4] = "avpll_a4",
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[AVPLL_A5] = "avpll_a5",
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[AVPLL_A6] = "avpll_a6",
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[AVPLL_A7] = "avpll_a7",
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[AVPLL_A8] = "avpll_a8",
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[AVPLL_B1] = "avpll_b1",
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[AVPLL_B2] = "avpll_b2",
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[AVPLL_B3] = "avpll_b3",
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[AVPLL_B4] = "avpll_b4",
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[AVPLL_B5] = "avpll_b5",
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[AVPLL_B6] = "avpll_b6",
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[AVPLL_B7] = "avpll_b7",
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[AVPLL_B8] = "avpll_b8",
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[AUDIO1_PLL] = "audio1_pll",
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[AUDIO_FAST_PLL] = "audio_fast_pll",
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[VIDEO0_PLL] = "video0_pll",
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[VIDEO0_IN] = "video0_in",
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[VIDEO1_PLL] = "video1_pll",
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[VIDEO1_IN] = "video1_in",
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[VIDEO2_PLL] = "video2_pll",
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[VIDEO2_IN] = "video2_in",
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};
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static const struct berlin2_pll_map bg2_pll_map __initconst = {
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.vcodiv = {10, 15, 20, 25, 30, 40, 50, 60, 80},
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.mult = 10,
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.fbdiv_shift = 6,
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.rfdiv_shift = 1,
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.divsel_shift = 7,
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};
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static const u8 default_parent_ids[] = {
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SYSPLL, AVPLL_B4, AVPLL_A5, AVPLL_B6, AVPLL_B7, SYSPLL
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};
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static const struct berlin2_div_data bg2_divs[] __initconst = {
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{
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.name = "sys",
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.parent_ids = (const u8 []){
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SYSPLL, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, SYSPLL
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},
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.num_parents = 6,
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 0),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 0),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 3),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 3),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 4),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 5),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = CLK_IGNORE_UNUSED,
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},
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{
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.name = "cpu",
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.parent_ids = (const u8 []){
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CPUPLL, MEMPLL, MEMPLL, MEMPLL, MEMPLL
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},
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.num_parents = 5,
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.map = {
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 6),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 9),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 6),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 7),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 8),
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},
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.div_flags = BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "drmfigo",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 16),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 17),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 20),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 12),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 13),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 14),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "cfg",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 1),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 23),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 26),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 15),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 16),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 17),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "gfx",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 4),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 29),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 0),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 18),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 19),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 20),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "zsp",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 5),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 3),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 6),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 21),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 22),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 23),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "perif",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 6),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 9),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 12),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 24),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 25),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 26),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = CLK_IGNORE_UNUSED,
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},
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{
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.name = "pcube",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 2),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 15),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 18),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 27),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 28),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 29),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "vscope",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 3),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 21),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 24),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 30),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 31),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 0),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "nfc_ecc",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 18),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 27),
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BERLIN2_DIV_SELECT(REG_CLKSELECT2, 0),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 1),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 2),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 3),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "vpp",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 21),
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BERLIN2_PLL_SELECT(REG_CLKSELECT2, 3),
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BERLIN2_DIV_SELECT(REG_CLKSELECT2, 6),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 4),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 5),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 6),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "app",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 20),
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BERLIN2_PLL_SELECT(REG_CLKSELECT2, 9),
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BERLIN2_DIV_SELECT(REG_CLKSELECT2, 12),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 7),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 8),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 9),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "audio0",
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.parent_ids = (const u8 []){ AUDIO_FAST_PLL },
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.num_parents = 1,
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 22),
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BERLIN2_DIV_SELECT(REG_CLKSELECT2, 17),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 10),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 11),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE,
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.flags = 0,
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},
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{
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.name = "audio2",
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.parent_ids = (const u8 []){ AUDIO_FAST_PLL },
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.num_parents = 1,
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 24),
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BERLIN2_DIV_SELECT(REG_CLKSELECT2, 20),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 14),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 15),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE,
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.flags = 0,
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},
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{
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.name = "audio3",
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.parent_ids = (const u8 []){ AUDIO_FAST_PLL },
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.num_parents = 1,
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 25),
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BERLIN2_DIV_SELECT(REG_CLKSELECT2, 23),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 16),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 17),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE,
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.flags = 0,
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},
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{
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.name = "audio1",
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.parent_ids = (const u8 []){ AUDIO1_PLL },
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.num_parents = 1,
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 23),
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BERLIN2_DIV_SELECT(REG_CLKSELECT3, 0),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 12),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 13),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE,
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.flags = 0,
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},
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{
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.name = "gfx3d_core",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_SINGLE_DIV(REG_GFX3DCORE_CLKCTL),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "gfx3d_sys",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_SINGLE_DIV(REG_GFX3DSYS_CLKCTL),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "arc",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_SINGLE_DIV(REG_ARC_CLKCTL),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "vip",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_SINGLE_DIV(REG_VIP_CLKCTL),
|
|
},
|
|
.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
|
|
.flags = 0,
|
|
},
|
|
{
|
|
.name = "sdio0xin",
|
|
.parent_ids = default_parent_ids,
|
|
.num_parents = ARRAY_SIZE(default_parent_ids),
|
|
.map = {
|
|
BERLIN2_SINGLE_DIV(REG_SDIO0XIN_CLKCTL),
|
|
},
|
|
.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
|
|
.flags = 0,
|
|
},
|
|
{
|
|
.name = "sdio1xin",
|
|
.parent_ids = default_parent_ids,
|
|
.num_parents = ARRAY_SIZE(default_parent_ids),
|
|
.map = {
|
|
BERLIN2_SINGLE_DIV(REG_SDIO1XIN_CLKCTL),
|
|
},
|
|
.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
|
|
.flags = 0,
|
|
},
|
|
{
|
|
.name = "gfx3d_extra",
|
|
.parent_ids = default_parent_ids,
|
|
.num_parents = ARRAY_SIZE(default_parent_ids),
|
|
.map = {
|
|
BERLIN2_SINGLE_DIV(REG_GFX3DEXTRA_CLKCTL),
|
|
},
|
|
.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
|
|
.flags = 0,
|
|
},
|
|
{
|
|
.name = "gc360",
|
|
.parent_ids = default_parent_ids,
|
|
.num_parents = ARRAY_SIZE(default_parent_ids),
|
|
.map = {
|
|
BERLIN2_SINGLE_DIV(REG_GC360_CLKCTL),
|
|
},
|
|
.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
|
|
.flags = 0,
|
|
},
|
|
{
|
|
.name = "sdio_dllmst",
|
|
.parent_ids = default_parent_ids,
|
|
.num_parents = ARRAY_SIZE(default_parent_ids),
|
|
.map = {
|
|
BERLIN2_SINGLE_DIV(REG_SDIO_DLLMST_CLKCTL),
|
|
},
|
|
.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
|
|
.flags = 0,
|
|
},
|
|
};
|
|
|
|
static const struct berlin2_gate_data bg2_gates[] __initconst = {
|
|
{ "geth0", "perif", 7 },
|
|
{ "geth1", "perif", 8 },
|
|
{ "sata", "perif", 9 },
|
|
{ "ahbapb", "perif", 10, CLK_IGNORE_UNUSED },
|
|
{ "usb0", "perif", 11 },
|
|
{ "usb1", "perif", 12 },
|
|
{ "pbridge", "perif", 13, CLK_IGNORE_UNUSED },
|
|
{ "sdio0", "perif", 14, CLK_IGNORE_UNUSED },
|
|
{ "sdio1", "perif", 15, CLK_IGNORE_UNUSED },
|
|
{ "nfc", "perif", 17 },
|
|
{ "smemc", "perif", 19 },
|
|
{ "audiohd", "audiohd_pll", 26 },
|
|
{ "video0", "video0_in", 27 },
|
|
{ "video1", "video1_in", 28 },
|
|
{ "video2", "video2_in", 29 },
|
|
};
|
|
|
|
static void __init berlin2_clock_setup(struct device_node *np)
|
|
{
|
|
struct device_node *parent_np = of_get_parent(np);
|
|
const char *parent_names[9];
|
|
struct clk *clk;
|
|
u8 avpll_flags = 0;
|
|
int n;
|
|
|
|
gbase = of_iomap(parent_np, 0);
|
|
if (!gbase)
|
|
return;
|
|
|
|
/* overwrite default clock names with DT provided ones */
|
|
clk = of_clk_get_by_name(np, clk_names[REFCLK]);
|
|
if (!IS_ERR(clk)) {
|
|
clk_names[REFCLK] = __clk_get_name(clk);
|
|
clk_put(clk);
|
|
}
|
|
|
|
clk = of_clk_get_by_name(np, clk_names[VIDEO_EXT0]);
|
|
if (!IS_ERR(clk)) {
|
|
clk_names[VIDEO_EXT0] = __clk_get_name(clk);
|
|
clk_put(clk);
|
|
}
|
|
|
|
/* simple register PLLs */
|
|
clk = berlin2_pll_register(&bg2_pll_map, gbase + REG_SYSPLLCTL0,
|
|
clk_names[SYSPLL], clk_names[REFCLK], 0);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
clk = berlin2_pll_register(&bg2_pll_map, gbase + REG_MEMPLLCTL0,
|
|
clk_names[MEMPLL], clk_names[REFCLK], 0);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
clk = berlin2_pll_register(&bg2_pll_map, gbase + REG_CPUPLLCTL0,
|
|
clk_names[CPUPLL], clk_names[REFCLK], 0);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
if (of_device_is_compatible(np, "marvell,berlin2-global-register"))
|
|
avpll_flags |= BERLIN2_AVPLL_SCRAMBLE_QUIRK;
|
|
|
|
/* audio/video VCOs */
|
|
clk = berlin2_avpll_vco_register(gbase + REG_AVPLLCTL0, "avpll_vcoA",
|
|
clk_names[REFCLK], avpll_flags, 0);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
for (n = 0; n < 8; n++) {
|
|
clk = berlin2_avpll_channel_register(gbase + REG_AVPLLCTL0,
|
|
clk_names[AVPLL_A1 + n], n, "avpll_vcoA",
|
|
avpll_flags, 0);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
}
|
|
|
|
clk = berlin2_avpll_vco_register(gbase + REG_AVPLLCTL31, "avpll_vcoB",
|
|
clk_names[REFCLK], BERLIN2_AVPLL_BIT_QUIRK |
|
|
avpll_flags, 0);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
for (n = 0; n < 8; n++) {
|
|
clk = berlin2_avpll_channel_register(gbase + REG_AVPLLCTL31,
|
|
clk_names[AVPLL_B1 + n], n, "avpll_vcoB",
|
|
BERLIN2_AVPLL_BIT_QUIRK | avpll_flags, 0);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
}
|
|
|
|
/* reference clock bypass switches */
|
|
parent_names[0] = clk_names[SYSPLL];
|
|
parent_names[1] = clk_names[REFCLK];
|
|
clk = clk_register_mux(NULL, "syspll_byp", parent_names, 2,
|
|
0, gbase + REG_CLKSWITCH0, 0, 1, 0, &lock);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
clk_names[SYSPLL] = __clk_get_name(clk);
|
|
|
|
parent_names[0] = clk_names[MEMPLL];
|
|
parent_names[1] = clk_names[REFCLK];
|
|
clk = clk_register_mux(NULL, "mempll_byp", parent_names, 2,
|
|
0, gbase + REG_CLKSWITCH0, 1, 1, 0, &lock);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
clk_names[MEMPLL] = __clk_get_name(clk);
|
|
|
|
parent_names[0] = clk_names[CPUPLL];
|
|
parent_names[1] = clk_names[REFCLK];
|
|
clk = clk_register_mux(NULL, "cpupll_byp", parent_names, 2,
|
|
0, gbase + REG_CLKSWITCH0, 2, 1, 0, &lock);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
clk_names[CPUPLL] = __clk_get_name(clk);
|
|
|
|
/* clock muxes */
|
|
parent_names[0] = clk_names[AVPLL_B3];
|
|
parent_names[1] = clk_names[AVPLL_A3];
|
|
clk = clk_register_mux(NULL, clk_names[AUDIO1_PLL], parent_names, 2,
|
|
0, gbase + REG_CLKSELECT2, 29, 1, 0, &lock);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
parent_names[0] = clk_names[VIDEO0_PLL];
|
|
parent_names[1] = clk_names[VIDEO_EXT0];
|
|
clk = clk_register_mux(NULL, clk_names[VIDEO0_IN], parent_names, 2,
|
|
0, gbase + REG_CLKSELECT3, 4, 1, 0, &lock);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
parent_names[0] = clk_names[VIDEO1_PLL];
|
|
parent_names[1] = clk_names[VIDEO_EXT0];
|
|
clk = clk_register_mux(NULL, clk_names[VIDEO1_IN], parent_names, 2,
|
|
0, gbase + REG_CLKSELECT3, 6, 1, 0, &lock);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
parent_names[0] = clk_names[AVPLL_A2];
|
|
parent_names[1] = clk_names[AVPLL_B2];
|
|
clk = clk_register_mux(NULL, clk_names[VIDEO1_PLL], parent_names, 2,
|
|
0, gbase + REG_CLKSELECT3, 7, 1, 0, &lock);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
parent_names[0] = clk_names[VIDEO2_PLL];
|
|
parent_names[1] = clk_names[VIDEO_EXT0];
|
|
clk = clk_register_mux(NULL, clk_names[VIDEO2_IN], parent_names, 2,
|
|
0, gbase + REG_CLKSELECT3, 9, 1, 0, &lock);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
parent_names[0] = clk_names[AVPLL_B1];
|
|
parent_names[1] = clk_names[AVPLL_A5];
|
|
clk = clk_register_mux(NULL, clk_names[VIDEO2_PLL], parent_names, 2,
|
|
0, gbase + REG_CLKSELECT3, 10, 1, 0, &lock);
|
|
if (IS_ERR(clk))
|
|
goto bg2_fail;
|
|
|
|
/* clock divider cells */
|
|
for (n = 0; n < ARRAY_SIZE(bg2_divs); n++) {
|
|
const struct berlin2_div_data *dd = &bg2_divs[n];
|
|
int k;
|
|
|
|
for (k = 0; k < dd->num_parents; k++)
|
|
parent_names[k] = clk_names[dd->parent_ids[k]];
|
|
|
|
clks[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase,
|
|
dd->name, dd->div_flags, parent_names,
|
|
dd->num_parents, dd->flags, &lock);
|
|
}
|
|
|
|
/* clock gate cells */
|
|
for (n = 0; n < ARRAY_SIZE(bg2_gates); n++) {
|
|
const struct berlin2_gate_data *gd = &bg2_gates[n];
|
|
|
|
clks[CLKID_GETH0 + n] = clk_register_gate(NULL, gd->name,
|
|
gd->parent_name, gd->flags, gbase + REG_CLKENABLE,
|
|
gd->bit_idx, 0, &lock);
|
|
}
|
|
|
|
/* twdclk is derived from cpu/3 */
|
|
clks[CLKID_TWD] =
|
|
clk_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
|
|
|
|
/* check for errors on leaf clocks */
|
|
for (n = 0; n < MAX_CLKS; n++) {
|
|
if (!IS_ERR(clks[n]))
|
|
continue;
|
|
|
|
pr_err("%s: Unable to register leaf clock %d\n",
|
|
np->full_name, n);
|
|
goto bg2_fail;
|
|
}
|
|
|
|
/* register clk-provider */
|
|
clk_data.clks = clks;
|
|
clk_data.clk_num = MAX_CLKS;
|
|
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
|
|
|
return;
|
|
|
|
bg2_fail:
|
|
iounmap(gbase);
|
|
}
|
|
CLK_OF_DECLARE(berlin2_clk, "marvell,berlin2-clk",
|
|
berlin2_clock_setup);
|