linux/arch/x86/events/amd
Janakarajan Natarajan ab027620e9 perf/x86/amd/uncore: Get correct number of cores sharing last level cache
In Family 17h, the number of cores sharing a cache level is obtained
from the Cache Properties CPUID leaf (0x8000001d) by passing in the
cache level in ECX. In prior families, a cache level of 2 was used to
determine this information.

To get the right information, irrespective of Family, iterate over
the cache levels using CPUID 0x8000001d. The last level cache is the
last value to return a non-zero value in EAX.

Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Borislav Petkov <bp@suse.de>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/5ab569025b39cdfaeca55b571d78c0fc800bdb69.1497452002.git.Janakarajan.Natarajan@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-08-10 12:08:39 +02:00
..
Makefile perf/x86/events: Add an AMD-specific Makefile 2017-01-30 12:01:19 +01:00
core.c x86/events: Remove last remnants of old filenames 2017-03-01 11:27:26 +01:00
ibs.c sched/headers: Prepare for new header dependencies before moving code to <linux/sched/clock.h> 2017-03-02 08:42:27 +01:00
iommu.c x86/events/amd/iommu: Enable support for multiple IOMMUs 2017-03-30 09:55:36 +02:00
iommu.h x86/events, drivers/amd/iommu: Prepare for multiple IOMMUs support 2017-03-30 09:53:55 +02:00
power.c cpu/hotplug: Cleanup state names 2016-12-25 10:47:44 +01:00
uncore.c perf/x86/amd/uncore: Get correct number of cores sharing last level cache 2017-08-10 12:08:39 +02:00