mirror of https://gitee.com/openkylin/linux.git
1120 lines
27 KiB
C
1120 lines
27 KiB
C
/**
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* core.c - DesignWare USB3 DRD Controller Core file
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/of.h>
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#include <linux/acpi.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/of.h>
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#include <linux/usb/otg.h>
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#include "platform_data.h"
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#include "core.h"
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#include "gadget.h"
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#include "io.h"
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#include "debug.h"
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/* -------------------------------------------------------------------------- */
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void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
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{
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u32 reg;
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
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reg |= DWC3_GCTL_PRTCAPDIR(mode);
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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}
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/**
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* dwc3_core_soft_reset - Issues core soft reset and PHY reset
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* @dwc: pointer to our context structure
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*/
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static int dwc3_core_soft_reset(struct dwc3 *dwc)
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{
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u32 reg;
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int ret;
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/* Before Resetting PHY, put Core in Reset */
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg |= DWC3_GCTL_CORESOFTRESET;
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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/* Assert USB3 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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/* Assert USB2 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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usb_phy_init(dwc->usb2_phy);
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usb_phy_init(dwc->usb3_phy);
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ret = phy_init(dwc->usb2_generic_phy);
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if (ret < 0)
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return ret;
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ret = phy_init(dwc->usb3_generic_phy);
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if (ret < 0) {
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phy_exit(dwc->usb2_generic_phy);
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return ret;
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}
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mdelay(100);
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/* Clear USB3 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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/* Clear USB2 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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mdelay(100);
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/* After PHYs are stable we can take Core out of reset state */
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~DWC3_GCTL_CORESOFTRESET;
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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return 0;
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}
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/**
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* dwc3_free_one_event_buffer - Frees one event buffer
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* @dwc: Pointer to our controller context structure
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* @evt: Pointer to event buffer to be freed
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*/
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static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
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struct dwc3_event_buffer *evt)
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{
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dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
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}
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/**
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* dwc3_alloc_one_event_buffer - Allocates one event buffer structure
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* @dwc: Pointer to our controller context structure
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* @length: size of the event buffer
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*
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* Returns a pointer to the allocated event buffer structure on success
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* otherwise ERR_PTR(errno).
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*/
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static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
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unsigned length)
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{
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struct dwc3_event_buffer *evt;
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evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
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if (!evt)
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return ERR_PTR(-ENOMEM);
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evt->dwc = dwc;
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evt->length = length;
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evt->buf = dma_alloc_coherent(dwc->dev, length,
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&evt->dma, GFP_KERNEL);
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if (!evt->buf)
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return ERR_PTR(-ENOMEM);
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return evt;
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}
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/**
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* dwc3_free_event_buffers - frees all allocated event buffers
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* @dwc: Pointer to our controller context structure
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*/
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static void dwc3_free_event_buffers(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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int i;
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for (i = 0; i < dwc->num_event_buffers; i++) {
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evt = dwc->ev_buffs[i];
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if (evt)
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dwc3_free_one_event_buffer(dwc, evt);
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}
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}
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/**
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* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
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* @dwc: pointer to our controller context structure
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* @length: size of event buffer
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*
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* Returns 0 on success otherwise negative errno. In the error case, dwc
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* may contain some buffers allocated but not all which were requested.
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*/
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static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
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{
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int num;
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int i;
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num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
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dwc->num_event_buffers = num;
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dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
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GFP_KERNEL);
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if (!dwc->ev_buffs)
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return -ENOMEM;
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for (i = 0; i < num; i++) {
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struct dwc3_event_buffer *evt;
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evt = dwc3_alloc_one_event_buffer(dwc, length);
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if (IS_ERR(evt)) {
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dev_err(dwc->dev, "can't allocate event buffer\n");
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return PTR_ERR(evt);
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}
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dwc->ev_buffs[i] = evt;
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}
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return 0;
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}
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/**
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* dwc3_event_buffers_setup - setup our allocated event buffers
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* @dwc: pointer to our controller context structure
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*
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* Returns 0 on success otherwise negative errno.
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*/
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static int dwc3_event_buffers_setup(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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int n;
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for (n = 0; n < dwc->num_event_buffers; n++) {
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evt = dwc->ev_buffs[n];
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dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
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evt->buf, (unsigned long long) evt->dma,
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evt->length);
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evt->lpos = 0;
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dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
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lower_32_bits(evt->dma));
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dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
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upper_32_bits(evt->dma));
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dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
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DWC3_GEVNTSIZ_SIZE(evt->length));
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dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
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}
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return 0;
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}
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static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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int n;
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for (n = 0; n < dwc->num_event_buffers; n++) {
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evt = dwc->ev_buffs[n];
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evt->lpos = 0;
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dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
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dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
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dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
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| DWC3_GEVNTSIZ_SIZE(0));
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dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
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}
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}
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static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
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{
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if (!dwc->has_hibernation)
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return 0;
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if (!dwc->nr_scratch)
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return 0;
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dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
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DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
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if (!dwc->scratchbuf)
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return -ENOMEM;
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return 0;
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}
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static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
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{
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dma_addr_t scratch_addr;
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u32 param;
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int ret;
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if (!dwc->has_hibernation)
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return 0;
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if (!dwc->nr_scratch)
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return 0;
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/* should never fall here */
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if (!WARN_ON(dwc->scratchbuf))
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return 0;
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scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
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dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
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DMA_BIDIRECTIONAL);
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if (dma_mapping_error(dwc->dev, scratch_addr)) {
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dev_err(dwc->dev, "failed to map scratch buffer\n");
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ret = -EFAULT;
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goto err0;
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}
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dwc->scratch_addr = scratch_addr;
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param = lower_32_bits(scratch_addr);
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ret = dwc3_send_gadget_generic_command(dwc,
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DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
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if (ret < 0)
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goto err1;
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param = upper_32_bits(scratch_addr);
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ret = dwc3_send_gadget_generic_command(dwc,
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DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
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if (ret < 0)
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goto err1;
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return 0;
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err1:
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dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
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DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
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err0:
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return ret;
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}
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static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
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{
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if (!dwc->has_hibernation)
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return;
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if (!dwc->nr_scratch)
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return;
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/* should never fall here */
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if (!WARN_ON(dwc->scratchbuf))
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return;
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dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
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DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
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kfree(dwc->scratchbuf);
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}
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static void dwc3_core_num_eps(struct dwc3 *dwc)
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{
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struct dwc3_hwparams *parms = &dwc->hwparams;
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dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
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dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
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dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
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dwc->num_in_eps, dwc->num_out_eps);
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}
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static void dwc3_cache_hwparams(struct dwc3 *dwc)
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{
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struct dwc3_hwparams *parms = &dwc->hwparams;
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parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
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parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
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parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
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parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
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parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
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parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
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parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
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parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
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parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
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}
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/**
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* dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
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* @dwc: Pointer to our controller context structure
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*/
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static void dwc3_phy_setup(struct dwc3 *dwc)
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{
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u32 reg;
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reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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/*
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* Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
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* to '0' during coreConsultant configuration. So default value
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* will be '0' when the core is reset. Application needs to set it
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* to '1' after the core initialization is completed.
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*/
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if (dwc->revision > DWC3_REVISION_194A)
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reg |= DWC3_GUSB3PIPECTL_SUSPHY;
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if (dwc->u2ss_inp3_quirk)
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reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
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if (dwc->req_p1p2p3_quirk)
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reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
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if (dwc->del_p1p2p3_quirk)
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reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
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if (dwc->del_phy_power_chg_quirk)
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reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
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if (dwc->lfps_filter_quirk)
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reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
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if (dwc->rx_detect_poll_quirk)
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reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
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|
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if (dwc->tx_de_emphasis_quirk)
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reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
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|
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if (dwc->dis_u3_susphy_quirk)
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reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
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|
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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|
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mdelay(100);
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|
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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|
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/*
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* Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
|
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* '0' during coreConsultant configuration. So default value will
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* be '0' when the core is reset. Application needs to set it to
|
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* '1' after the core initialization is completed.
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*/
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if (dwc->revision > DWC3_REVISION_194A)
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reg |= DWC3_GUSB2PHYCFG_SUSPHY;
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|
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if (dwc->dis_u2_susphy_quirk)
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reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
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|
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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|
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mdelay(100);
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}
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|
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/**
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* dwc3_core_init - Low-level initialization of DWC3 Core
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* @dwc: Pointer to our controller context structure
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*
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* Returns 0 on success otherwise negative errno.
|
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*/
|
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static int dwc3_core_init(struct dwc3 *dwc)
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{
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unsigned long timeout;
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u32 hwparams4 = dwc->hwparams.hwparams4;
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u32 reg;
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int ret;
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|
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reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
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/* This should read as U3 followed by revision number */
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if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
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dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
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ret = -ENODEV;
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goto err0;
|
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}
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dwc->revision = reg;
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|
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/*
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* Write Linux Version Code to our GUID register so it's easy to figure
|
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* out which kernel version a bug was found.
|
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*/
|
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dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
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|
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/* Handle USB2.0-only core configuration */
|
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if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
|
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DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
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if (dwc->maximum_speed == USB_SPEED_SUPER)
|
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dwc->maximum_speed = USB_SPEED_HIGH;
|
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}
|
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|
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/* issue device SoftReset too */
|
|
timeout = jiffies + msecs_to_jiffies(500);
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
|
|
do {
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
if (!(reg & DWC3_DCTL_CSFTRST))
|
|
break;
|
|
|
|
if (time_after(jiffies, timeout)) {
|
|
dev_err(dwc->dev, "Reset Timed Out\n");
|
|
ret = -ETIMEDOUT;
|
|
goto err0;
|
|
}
|
|
|
|
cpu_relax();
|
|
} while (true);
|
|
|
|
ret = dwc3_core_soft_reset(dwc);
|
|
if (ret)
|
|
goto err0;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
|
|
|
|
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
|
|
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
|
|
/**
|
|
* WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
|
|
* issue which would cause xHCI compliance tests to fail.
|
|
*
|
|
* Because of that we cannot enable clock gating on such
|
|
* configurations.
|
|
*
|
|
* Refers to:
|
|
*
|
|
* STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
|
|
* SOF/ITP Mode Used
|
|
*/
|
|
if ((dwc->dr_mode == USB_DR_MODE_HOST ||
|
|
dwc->dr_mode == USB_DR_MODE_OTG) &&
|
|
(dwc->revision >= DWC3_REVISION_210A &&
|
|
dwc->revision <= DWC3_REVISION_250A))
|
|
reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
|
|
else
|
|
reg &= ~DWC3_GCTL_DSBLCLKGTNG;
|
|
break;
|
|
case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
|
|
/* enable hibernation here */
|
|
dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
|
|
|
|
/*
|
|
* REVISIT Enabling this bit so that host-mode hibernation
|
|
* will work. Device-mode hibernation is not yet implemented.
|
|
*/
|
|
reg |= DWC3_GCTL_GBLHIBERNATIONEN;
|
|
break;
|
|
default:
|
|
dev_dbg(dwc->dev, "No power optimization available\n");
|
|
}
|
|
|
|
/* check if current dwc3 is on simulation board */
|
|
if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
|
|
dev_dbg(dwc->dev, "it is on FPGA board\n");
|
|
dwc->is_fpga = true;
|
|
}
|
|
|
|
WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
|
|
"disable_scramble cannot be used on non-FPGA builds\n");
|
|
|
|
if (dwc->disable_scramble_quirk && dwc->is_fpga)
|
|
reg |= DWC3_GCTL_DISSCRAMBLE;
|
|
else
|
|
reg &= ~DWC3_GCTL_DISSCRAMBLE;
|
|
|
|
if (dwc->u2exit_lfps_quirk)
|
|
reg |= DWC3_GCTL_U2EXIT_LFPS;
|
|
|
|
/*
|
|
* WORKAROUND: DWC3 revisions <1.90a have a bug
|
|
* where the device can fail to connect at SuperSpeed
|
|
* and falls back to high-speed mode which causes
|
|
* the device to enter a Connect/Disconnect loop
|
|
*/
|
|
if (dwc->revision < DWC3_REVISION_190A)
|
|
reg |= DWC3_GCTL_U2RSTECN;
|
|
|
|
dwc3_core_num_eps(dwc);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
|
|
dwc3_phy_setup(dwc);
|
|
|
|
ret = dwc3_alloc_scratch_buffers(dwc);
|
|
if (ret)
|
|
goto err1;
|
|
|
|
ret = dwc3_setup_scratch_buffers(dwc);
|
|
if (ret)
|
|
goto err2;
|
|
|
|
return 0;
|
|
|
|
err2:
|
|
dwc3_free_scratch_buffers(dwc);
|
|
|
|
err1:
|
|
usb_phy_shutdown(dwc->usb2_phy);
|
|
usb_phy_shutdown(dwc->usb3_phy);
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
phy_exit(dwc->usb3_generic_phy);
|
|
|
|
err0:
|
|
return ret;
|
|
}
|
|
|
|
static void dwc3_core_exit(struct dwc3 *dwc)
|
|
{
|
|
dwc3_free_scratch_buffers(dwc);
|
|
usb_phy_shutdown(dwc->usb2_phy);
|
|
usb_phy_shutdown(dwc->usb3_phy);
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
phy_exit(dwc->usb3_generic_phy);
|
|
}
|
|
|
|
static int dwc3_core_get_phy(struct dwc3 *dwc)
|
|
{
|
|
struct device *dev = dwc->dev;
|
|
struct device_node *node = dev->of_node;
|
|
int ret;
|
|
|
|
if (node) {
|
|
dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
|
|
dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
|
|
} else {
|
|
dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
|
|
dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
|
|
}
|
|
|
|
if (IS_ERR(dwc->usb2_phy)) {
|
|
ret = PTR_ERR(dwc->usb2_phy);
|
|
if (ret == -ENXIO || ret == -ENODEV) {
|
|
dwc->usb2_phy = NULL;
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
return ret;
|
|
} else {
|
|
dev_err(dev, "no usb2 phy configured\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (IS_ERR(dwc->usb3_phy)) {
|
|
ret = PTR_ERR(dwc->usb3_phy);
|
|
if (ret == -ENXIO || ret == -ENODEV) {
|
|
dwc->usb3_phy = NULL;
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
return ret;
|
|
} else {
|
|
dev_err(dev, "no usb3 phy configured\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
|
|
if (IS_ERR(dwc->usb2_generic_phy)) {
|
|
ret = PTR_ERR(dwc->usb2_generic_phy);
|
|
if (ret == -ENOSYS || ret == -ENODEV) {
|
|
dwc->usb2_generic_phy = NULL;
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
return ret;
|
|
} else {
|
|
dev_err(dev, "no usb2 phy configured\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
|
|
if (IS_ERR(dwc->usb3_generic_phy)) {
|
|
ret = PTR_ERR(dwc->usb3_generic_phy);
|
|
if (ret == -ENOSYS || ret == -ENODEV) {
|
|
dwc->usb3_generic_phy = NULL;
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
return ret;
|
|
} else {
|
|
dev_err(dev, "no usb3 phy configured\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_core_init_mode(struct dwc3 *dwc)
|
|
{
|
|
struct device *dev = dwc->dev;
|
|
int ret;
|
|
|
|
switch (dwc->dr_mode) {
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
|
|
ret = dwc3_gadget_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize gadget\n");
|
|
return ret;
|
|
}
|
|
break;
|
|
case USB_DR_MODE_HOST:
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
|
|
ret = dwc3_host_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize host\n");
|
|
return ret;
|
|
}
|
|
break;
|
|
case USB_DR_MODE_OTG:
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
|
|
ret = dwc3_host_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize host\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = dwc3_gadget_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize gadget\n");
|
|
return ret;
|
|
}
|
|
break;
|
|
default:
|
|
dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dwc3_core_exit_mode(struct dwc3 *dwc)
|
|
{
|
|
switch (dwc->dr_mode) {
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
dwc3_gadget_exit(dwc);
|
|
break;
|
|
case USB_DR_MODE_HOST:
|
|
dwc3_host_exit(dwc);
|
|
break;
|
|
case USB_DR_MODE_OTG:
|
|
dwc3_host_exit(dwc);
|
|
dwc3_gadget_exit(dwc);
|
|
break;
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
}
|
|
|
|
#define DWC3_ALIGN_MASK (16 - 1)
|
|
|
|
static int dwc3_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct dwc3_platform_data *pdata = dev_get_platdata(dev);
|
|
struct device_node *node = dev->of_node;
|
|
struct resource *res;
|
|
struct dwc3 *dwc;
|
|
u8 lpm_nyet_threshold;
|
|
u8 tx_de_emphasis;
|
|
u8 hird_threshold;
|
|
|
|
int ret;
|
|
|
|
void __iomem *regs;
|
|
void *mem;
|
|
|
|
mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
|
|
if (!mem)
|
|
return -ENOMEM;
|
|
|
|
dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
|
|
dwc->mem = mem;
|
|
dwc->dev = dev;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (!res) {
|
|
dev_err(dev, "missing IRQ\n");
|
|
return -ENODEV;
|
|
}
|
|
dwc->xhci_resources[1].start = res->start;
|
|
dwc->xhci_resources[1].end = res->end;
|
|
dwc->xhci_resources[1].flags = res->flags;
|
|
dwc->xhci_resources[1].name = res->name;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(dev, "missing memory resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
dwc->xhci_resources[0].start = res->start;
|
|
dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
|
|
DWC3_XHCI_REGS_END;
|
|
dwc->xhci_resources[0].flags = res->flags;
|
|
dwc->xhci_resources[0].name = res->name;
|
|
|
|
res->start += DWC3_GLOBALS_REGS_START;
|
|
|
|
/*
|
|
* Request memory region but exclude xHCI regs,
|
|
* since it will be requested by the xhci-plat driver.
|
|
*/
|
|
regs = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
|
|
dwc->regs = regs;
|
|
dwc->regs_size = resource_size(res);
|
|
/*
|
|
* restore res->start back to its original value so that,
|
|
* in case the probe is deferred, we don't end up getting error in
|
|
* request the memory region the next time probe is called.
|
|
*/
|
|
res->start -= DWC3_GLOBALS_REGS_START;
|
|
|
|
/* default to highest possible threshold */
|
|
lpm_nyet_threshold = 0xff;
|
|
|
|
/* default to -3.5dB de-emphasis */
|
|
tx_de_emphasis = 1;
|
|
|
|
/*
|
|
* default to assert utmi_sleep_n and use maximum allowed HIRD
|
|
* threshold value of 0b1100
|
|
*/
|
|
hird_threshold = 12;
|
|
|
|
if (node) {
|
|
dwc->maximum_speed = of_usb_get_maximum_speed(node);
|
|
dwc->has_lpm_erratum = of_property_read_bool(node,
|
|
"snps,has-lpm-erratum");
|
|
of_property_read_u8(node, "snps,lpm-nyet-threshold",
|
|
&lpm_nyet_threshold);
|
|
dwc->is_utmi_l1_suspend = of_property_read_bool(node,
|
|
"snps,is-utmi-l1-suspend");
|
|
of_property_read_u8(node, "snps,hird-threshold",
|
|
&hird_threshold);
|
|
|
|
dwc->needs_fifo_resize = of_property_read_bool(node,
|
|
"tx-fifo-resize");
|
|
dwc->dr_mode = of_usb_get_dr_mode(node);
|
|
|
|
dwc->disable_scramble_quirk = of_property_read_bool(node,
|
|
"snps,disable_scramble_quirk");
|
|
dwc->u2exit_lfps_quirk = of_property_read_bool(node,
|
|
"snps,u2exit_lfps_quirk");
|
|
dwc->u2ss_inp3_quirk = of_property_read_bool(node,
|
|
"snps,u2ss_inp3_quirk");
|
|
dwc->req_p1p2p3_quirk = of_property_read_bool(node,
|
|
"snps,req_p1p2p3_quirk");
|
|
dwc->del_p1p2p3_quirk = of_property_read_bool(node,
|
|
"snps,del_p1p2p3_quirk");
|
|
dwc->del_phy_power_chg_quirk = of_property_read_bool(node,
|
|
"snps,del_phy_power_chg_quirk");
|
|
dwc->lfps_filter_quirk = of_property_read_bool(node,
|
|
"snps,lfps_filter_quirk");
|
|
dwc->rx_detect_poll_quirk = of_property_read_bool(node,
|
|
"snps,rx_detect_poll_quirk");
|
|
dwc->dis_u3_susphy_quirk = of_property_read_bool(node,
|
|
"snps,dis_u3_susphy_quirk");
|
|
dwc->dis_u2_susphy_quirk = of_property_read_bool(node,
|
|
"snps,dis_u2_susphy_quirk");
|
|
|
|
dwc->tx_de_emphasis_quirk = of_property_read_bool(node,
|
|
"snps,tx_de_emphasis_quirk");
|
|
of_property_read_u8(node, "snps,tx_de_emphasis",
|
|
&tx_de_emphasis);
|
|
} else if (pdata) {
|
|
dwc->maximum_speed = pdata->maximum_speed;
|
|
dwc->has_lpm_erratum = pdata->has_lpm_erratum;
|
|
if (pdata->lpm_nyet_threshold)
|
|
lpm_nyet_threshold = pdata->lpm_nyet_threshold;
|
|
dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
|
|
if (pdata->hird_threshold)
|
|
hird_threshold = pdata->hird_threshold;
|
|
|
|
dwc->needs_fifo_resize = pdata->tx_fifo_resize;
|
|
dwc->dr_mode = pdata->dr_mode;
|
|
|
|
dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
|
|
dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
|
|
dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
|
|
dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
|
|
dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
|
|
dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
|
|
dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
|
|
dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
|
|
dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
|
|
dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
|
|
|
|
dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
|
|
if (pdata->tx_de_emphasis)
|
|
tx_de_emphasis = pdata->tx_de_emphasis;
|
|
}
|
|
|
|
/* default to superspeed if no maximum_speed passed */
|
|
if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
|
|
dwc->maximum_speed = USB_SPEED_SUPER;
|
|
|
|
dwc->lpm_nyet_threshold = lpm_nyet_threshold;
|
|
dwc->tx_de_emphasis = tx_de_emphasis;
|
|
|
|
dwc->hird_threshold = hird_threshold
|
|
| (dwc->is_utmi_l1_suspend << 4);
|
|
|
|
ret = dwc3_core_get_phy(dwc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
spin_lock_init(&dwc->lock);
|
|
platform_set_drvdata(pdev, dwc);
|
|
|
|
if (!dev->dma_mask) {
|
|
dev->dma_mask = dev->parent->dma_mask;
|
|
dev->dma_parms = dev->parent->dma_parms;
|
|
dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_get_sync(dev);
|
|
pm_runtime_forbid(dev);
|
|
|
|
dwc3_cache_hwparams(dwc);
|
|
|
|
ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to allocate event buffers\n");
|
|
ret = -ENOMEM;
|
|
goto err0;
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
|
|
dwc->dr_mode = USB_DR_MODE_HOST;
|
|
else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
|
|
dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
|
|
|
|
if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
|
|
dwc->dr_mode = USB_DR_MODE_OTG;
|
|
|
|
ret = dwc3_core_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize core\n");
|
|
goto err0;
|
|
}
|
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 0);
|
|
usb_phy_set_suspend(dwc->usb3_phy, 0);
|
|
ret = phy_power_on(dwc->usb2_generic_phy);
|
|
if (ret < 0)
|
|
goto err1;
|
|
|
|
ret = phy_power_on(dwc->usb3_generic_phy);
|
|
if (ret < 0)
|
|
goto err_usb2phy_power;
|
|
|
|
ret = dwc3_event_buffers_setup(dwc);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to setup event buffers\n");
|
|
goto err_usb3phy_power;
|
|
}
|
|
|
|
ret = dwc3_core_init_mode(dwc);
|
|
if (ret)
|
|
goto err2;
|
|
|
|
ret = dwc3_debugfs_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize debugfs\n");
|
|
goto err3;
|
|
}
|
|
|
|
pm_runtime_allow(dev);
|
|
|
|
return 0;
|
|
|
|
err3:
|
|
dwc3_core_exit_mode(dwc);
|
|
|
|
err2:
|
|
dwc3_event_buffers_cleanup(dwc);
|
|
|
|
err_usb3phy_power:
|
|
phy_power_off(dwc->usb3_generic_phy);
|
|
|
|
err_usb2phy_power:
|
|
phy_power_off(dwc->usb2_generic_phy);
|
|
|
|
err1:
|
|
usb_phy_set_suspend(dwc->usb2_phy, 1);
|
|
usb_phy_set_suspend(dwc->usb3_phy, 1);
|
|
dwc3_core_exit(dwc);
|
|
|
|
err0:
|
|
dwc3_free_event_buffers(dwc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_remove(struct platform_device *pdev)
|
|
{
|
|
struct dwc3 *dwc = platform_get_drvdata(pdev);
|
|
|
|
dwc3_debugfs_exit(dwc);
|
|
dwc3_core_exit_mode(dwc);
|
|
dwc3_event_buffers_cleanup(dwc);
|
|
dwc3_free_event_buffers(dwc);
|
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 1);
|
|
usb_phy_set_suspend(dwc->usb3_phy, 1);
|
|
phy_power_off(dwc->usb2_generic_phy);
|
|
phy_power_off(dwc->usb3_generic_phy);
|
|
|
|
dwc3_core_exit(dwc);
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int dwc3_suspend(struct device *dev)
|
|
{
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
switch (dwc->dr_mode) {
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
case USB_DR_MODE_OTG:
|
|
dwc3_gadget_suspend(dwc);
|
|
/* FALLTHROUGH */
|
|
case USB_DR_MODE_HOST:
|
|
default:
|
|
dwc3_event_buffers_cleanup(dwc);
|
|
break;
|
|
}
|
|
|
|
dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
usb_phy_shutdown(dwc->usb3_phy);
|
|
usb_phy_shutdown(dwc->usb2_phy);
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
phy_exit(dwc->usb3_generic_phy);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_resume(struct device *dev)
|
|
{
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
usb_phy_init(dwc->usb3_phy);
|
|
usb_phy_init(dwc->usb2_phy);
|
|
ret = phy_init(dwc->usb2_generic_phy);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = phy_init(dwc->usb3_generic_phy);
|
|
if (ret < 0)
|
|
goto err_usb2phy_init;
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
dwc3_event_buffers_setup(dwc);
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
|
|
|
|
switch (dwc->dr_mode) {
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
case USB_DR_MODE_OTG:
|
|
dwc3_gadget_resume(dwc);
|
|
/* FALLTHROUGH */
|
|
case USB_DR_MODE_HOST:
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
|
|
return 0;
|
|
|
|
err_usb2phy_init:
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops dwc3_dev_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
|
|
};
|
|
|
|
#define DWC3_PM_OPS &(dwc3_dev_pm_ops)
|
|
#else
|
|
#define DWC3_PM_OPS NULL
|
|
#endif
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id of_dwc3_match[] = {
|
|
{
|
|
.compatible = "snps,dwc3"
|
|
},
|
|
{
|
|
.compatible = "synopsys,dwc3"
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, of_dwc3_match);
|
|
#endif
|
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
#define ACPI_ID_INTEL_BSW "808622B7"
|
|
|
|
static const struct acpi_device_id dwc3_acpi_match[] = {
|
|
{ ACPI_ID_INTEL_BSW, 0 },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
|
|
#endif
|
|
|
|
static struct platform_driver dwc3_driver = {
|
|
.probe = dwc3_probe,
|
|
.remove = dwc3_remove,
|
|
.driver = {
|
|
.name = "dwc3",
|
|
.of_match_table = of_match_ptr(of_dwc3_match),
|
|
.acpi_match_table = ACPI_PTR(dwc3_acpi_match),
|
|
.pm = DWC3_PM_OPS,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(dwc3_driver);
|
|
|
|
MODULE_ALIAS("platform:dwc3");
|
|
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
|