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62 lines
2.3 KiB
Plaintext
62 lines
2.3 KiB
Plaintext
* Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
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UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
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Each UFS PHY node should have its own node.
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To bind UFS PHY with UFS host controller, the controller node should
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contain a phandle reference to UFS PHY node.
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Required properties:
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- compatible : compatible list, contains one of the following -
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"qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
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"qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
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"qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
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present on MSM8996 chipset.
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- reg : should contain PHY register address space (mandatory),
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- reg-names : indicates various resources passed to driver (via reg proptery) by name.
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Required "reg-names" is "phy_mem".
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- #phy-cells : This property shall be set to 0
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- vdda-phy-supply : phandle to main PHY supply for analog domain
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- vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
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- clocks : List of phandle and clock specifier pairs
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- clock-names : List of clock input name strings sorted in the same
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order as the clocks property. "ref_clk_src", "ref_clk",
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"tx_iface_clk" & "rx_iface_clk" are mandatory but
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"ref_clk_parent" is optional
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Optional properties:
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- vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply
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- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
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- vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply
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- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
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- vddp-ref-clk-always-on : specifies if this supply needs to be kept always on
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Example:
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ufsphy1: ufsphy@0xfc597000 {
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compatible = "qcom,ufs-phy-qmp-20nm";
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reg = <0xfc597000 0x800>;
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reg-names = "phy_mem";
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#phy-cells = <0>;
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vdda-phy-supply = <&pma8084_l4>;
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vdda-pll-supply = <&pma8084_l12>;
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vdda-phy-max-microamp = <50000>;
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vdda-pll-max-microamp = <1000>;
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clock-names = "ref_clk_src",
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"ref_clk_parent",
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"ref_clk",
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"tx_iface_clk",
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"rx_iface_clk";
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clocks = <&clock_rpm clk_ln_bb_clk>,
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<&clock_gcc clk_pcie_1_phy_ldo >,
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<&clock_gcc clk_ufs_phy_ldo>,
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<&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
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<&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
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};
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ufshc@0xfc598000 {
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...
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phys = <&ufsphy1>;
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phy-names = "ufsphy";
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};
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