mirror of https://gitee.com/openkylin/linux.git
1378 lines
33 KiB
C
1378 lines
33 KiB
C
/*
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* Copyright (C) 2013 Huawei Ltd.
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* Author: Jiang Liu <liuj97@gmail.com>
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*
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* Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/stop_machine.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include <asm/cacheflush.h>
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#include <asm/debug-monitors.h>
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#include <asm/fixmap.h>
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#include <asm/insn.h>
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#include <asm/kprobes.h>
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#define AARCH64_INSN_SF_BIT BIT(31)
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#define AARCH64_INSN_N_BIT BIT(22)
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static int aarch64_insn_encoding_class[] = {
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AARCH64_INSN_CLS_UNKNOWN,
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AARCH64_INSN_CLS_UNKNOWN,
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AARCH64_INSN_CLS_UNKNOWN,
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AARCH64_INSN_CLS_UNKNOWN,
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AARCH64_INSN_CLS_LDST,
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AARCH64_INSN_CLS_DP_REG,
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AARCH64_INSN_CLS_LDST,
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AARCH64_INSN_CLS_DP_FPSIMD,
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AARCH64_INSN_CLS_DP_IMM,
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AARCH64_INSN_CLS_DP_IMM,
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AARCH64_INSN_CLS_BR_SYS,
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AARCH64_INSN_CLS_BR_SYS,
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AARCH64_INSN_CLS_LDST,
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AARCH64_INSN_CLS_DP_REG,
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AARCH64_INSN_CLS_LDST,
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AARCH64_INSN_CLS_DP_FPSIMD,
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};
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enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
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{
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return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
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}
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/* NOP is an alias of HINT */
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bool __kprobes aarch64_insn_is_nop(u32 insn)
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{
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if (!aarch64_insn_is_hint(insn))
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return false;
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switch (insn & 0xFE0) {
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case AARCH64_INSN_HINT_YIELD:
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case AARCH64_INSN_HINT_WFE:
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case AARCH64_INSN_HINT_WFI:
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case AARCH64_INSN_HINT_SEV:
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case AARCH64_INSN_HINT_SEVL:
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return false;
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default:
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return true;
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}
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}
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bool aarch64_insn_is_branch_imm(u32 insn)
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{
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return (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn) ||
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aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn) ||
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aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
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aarch64_insn_is_bcond(insn));
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}
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static DEFINE_RAW_SPINLOCK(patch_lock);
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static void __kprobes *patch_map(void *addr, int fixmap)
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{
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unsigned long uintaddr = (uintptr_t) addr;
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bool module = !core_kernel_text(uintaddr);
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struct page *page;
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if (module && IS_ENABLED(CONFIG_STRICT_MODULE_RWX))
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page = vmalloc_to_page(addr);
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else if (!module)
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page = phys_to_page(__pa_symbol(addr));
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else
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return addr;
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BUG_ON(!page);
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return (void *)set_fixmap_offset(fixmap, page_to_phys(page) +
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(uintaddr & ~PAGE_MASK));
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}
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static void __kprobes patch_unmap(int fixmap)
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{
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clear_fixmap(fixmap);
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}
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/*
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* In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
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* little-endian.
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*/
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int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
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{
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int ret;
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u32 val;
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ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
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if (!ret)
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*insnp = le32_to_cpu(val);
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return ret;
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}
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static int __kprobes __aarch64_insn_write(void *addr, u32 insn)
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{
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void *waddr = addr;
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unsigned long flags = 0;
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int ret;
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raw_spin_lock_irqsave(&patch_lock, flags);
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waddr = patch_map(addr, FIX_TEXT_POKE0);
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ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE);
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patch_unmap(FIX_TEXT_POKE0);
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raw_spin_unlock_irqrestore(&patch_lock, flags);
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return ret;
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}
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int __kprobes aarch64_insn_write(void *addr, u32 insn)
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{
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insn = cpu_to_le32(insn);
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return __aarch64_insn_write(addr, insn);
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}
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static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
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{
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if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
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return false;
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return aarch64_insn_is_b(insn) ||
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aarch64_insn_is_bl(insn) ||
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aarch64_insn_is_svc(insn) ||
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aarch64_insn_is_hvc(insn) ||
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aarch64_insn_is_smc(insn) ||
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aarch64_insn_is_brk(insn) ||
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aarch64_insn_is_nop(insn);
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}
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bool __kprobes aarch64_insn_uses_literal(u32 insn)
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{
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/* ldr/ldrsw (literal), prfm */
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return aarch64_insn_is_ldr_lit(insn) ||
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aarch64_insn_is_ldrsw_lit(insn) ||
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aarch64_insn_is_adr_adrp(insn) ||
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aarch64_insn_is_prfm_lit(insn);
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}
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bool __kprobes aarch64_insn_is_branch(u32 insn)
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{
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/* b, bl, cb*, tb*, b.cond, br, blr */
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return aarch64_insn_is_b(insn) ||
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aarch64_insn_is_bl(insn) ||
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aarch64_insn_is_cbz(insn) ||
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aarch64_insn_is_cbnz(insn) ||
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aarch64_insn_is_tbz(insn) ||
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aarch64_insn_is_tbnz(insn) ||
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aarch64_insn_is_ret(insn) ||
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aarch64_insn_is_br(insn) ||
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aarch64_insn_is_blr(insn) ||
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aarch64_insn_is_bcond(insn);
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}
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/*
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* ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
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* Section B2.6.5 "Concurrent modification and execution of instructions":
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* Concurrent modification and execution of instructions can lead to the
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* resulting instruction performing any behavior that can be achieved by
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* executing any sequence of instructions that can be executed from the
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* same Exception level, except where the instruction before modification
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* and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
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* or SMC instruction.
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*/
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bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
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{
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return __aarch64_insn_hotpatch_safe(old_insn) &&
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__aarch64_insn_hotpatch_safe(new_insn);
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}
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int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
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{
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u32 *tp = addr;
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int ret;
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/* A64 instructions must be word aligned */
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if ((uintptr_t)tp & 0x3)
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return -EINVAL;
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ret = aarch64_insn_write(tp, insn);
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if (ret == 0)
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flush_icache_range((uintptr_t)tp,
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(uintptr_t)tp + AARCH64_INSN_SIZE);
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return ret;
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}
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struct aarch64_insn_patch {
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void **text_addrs;
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u32 *new_insns;
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int insn_cnt;
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atomic_t cpu_count;
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};
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static int __kprobes aarch64_insn_patch_text_cb(void *arg)
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{
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int i, ret = 0;
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struct aarch64_insn_patch *pp = arg;
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/* The first CPU becomes master */
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if (atomic_inc_return(&pp->cpu_count) == 1) {
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for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
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ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
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pp->new_insns[i]);
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/*
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* aarch64_insn_patch_text_nosync() calls flush_icache_range(),
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* which ends with "dsb; isb" pair guaranteeing global
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* visibility.
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*/
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/* Notify other processors with an additional increment. */
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atomic_inc(&pp->cpu_count);
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} else {
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while (atomic_read(&pp->cpu_count) <= num_online_cpus())
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cpu_relax();
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isb();
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}
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return ret;
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}
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int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
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{
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struct aarch64_insn_patch patch = {
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.text_addrs = addrs,
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.new_insns = insns,
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.insn_cnt = cnt,
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.cpu_count = ATOMIC_INIT(0),
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};
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if (cnt <= 0)
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return -EINVAL;
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return stop_machine(aarch64_insn_patch_text_cb, &patch,
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cpu_online_mask);
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}
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int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
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{
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int ret;
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u32 insn;
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/* Unsafe to patch multiple instructions without synchronizaiton */
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if (cnt == 1) {
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ret = aarch64_insn_read(addrs[0], &insn);
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if (ret)
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return ret;
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if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
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/*
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* ARMv8 architecture doesn't guarantee all CPUs see
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* the new instruction after returning from function
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* aarch64_insn_patch_text_nosync(). So send IPIs to
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* all other CPUs to achieve instruction
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* synchronization.
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*/
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ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
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kick_all_cpus_sync();
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return ret;
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}
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}
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return aarch64_insn_patch_text_sync(addrs, insns, cnt);
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}
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static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,
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u32 *maskp, int *shiftp)
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{
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u32 mask;
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int shift;
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switch (type) {
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case AARCH64_INSN_IMM_26:
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mask = BIT(26) - 1;
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shift = 0;
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break;
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case AARCH64_INSN_IMM_19:
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mask = BIT(19) - 1;
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shift = 5;
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break;
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case AARCH64_INSN_IMM_16:
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mask = BIT(16) - 1;
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shift = 5;
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break;
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case AARCH64_INSN_IMM_14:
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mask = BIT(14) - 1;
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shift = 5;
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break;
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case AARCH64_INSN_IMM_12:
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mask = BIT(12) - 1;
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shift = 10;
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break;
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case AARCH64_INSN_IMM_9:
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mask = BIT(9) - 1;
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shift = 12;
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break;
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case AARCH64_INSN_IMM_7:
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mask = BIT(7) - 1;
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shift = 15;
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break;
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case AARCH64_INSN_IMM_6:
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case AARCH64_INSN_IMM_S:
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mask = BIT(6) - 1;
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shift = 10;
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break;
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case AARCH64_INSN_IMM_R:
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mask = BIT(6) - 1;
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shift = 16;
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break;
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default:
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return -EINVAL;
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}
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*maskp = mask;
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*shiftp = shift;
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return 0;
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}
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#define ADR_IMM_HILOSPLIT 2
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#define ADR_IMM_SIZE SZ_2M
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#define ADR_IMM_LOMASK ((1 << ADR_IMM_HILOSPLIT) - 1)
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#define ADR_IMM_HIMASK ((ADR_IMM_SIZE >> ADR_IMM_HILOSPLIT) - 1)
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#define ADR_IMM_LOSHIFT 29
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#define ADR_IMM_HISHIFT 5
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u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn)
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{
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u32 immlo, immhi, mask;
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int shift;
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switch (type) {
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case AARCH64_INSN_IMM_ADR:
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shift = 0;
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immlo = (insn >> ADR_IMM_LOSHIFT) & ADR_IMM_LOMASK;
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immhi = (insn >> ADR_IMM_HISHIFT) & ADR_IMM_HIMASK;
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insn = (immhi << ADR_IMM_HILOSPLIT) | immlo;
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mask = ADR_IMM_SIZE - 1;
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break;
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default:
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if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
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pr_err("aarch64_insn_decode_immediate: unknown immediate encoding %d\n",
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type);
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return 0;
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}
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}
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return (insn >> shift) & mask;
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}
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u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
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u32 insn, u64 imm)
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{
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u32 immlo, immhi, mask;
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int shift;
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if (insn == AARCH64_BREAK_FAULT)
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return AARCH64_BREAK_FAULT;
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switch (type) {
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case AARCH64_INSN_IMM_ADR:
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shift = 0;
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immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT;
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imm >>= ADR_IMM_HILOSPLIT;
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immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT;
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imm = immlo | immhi;
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mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) |
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(ADR_IMM_HIMASK << ADR_IMM_HISHIFT));
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break;
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default:
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if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
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pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
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type);
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return AARCH64_BREAK_FAULT;
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}
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}
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/* Update the immediate field. */
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insn &= ~(mask << shift);
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insn |= (imm & mask) << shift;
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return insn;
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}
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u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
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u32 insn)
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{
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int shift;
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switch (type) {
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case AARCH64_INSN_REGTYPE_RT:
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case AARCH64_INSN_REGTYPE_RD:
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shift = 0;
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break;
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case AARCH64_INSN_REGTYPE_RN:
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shift = 5;
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break;
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case AARCH64_INSN_REGTYPE_RT2:
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case AARCH64_INSN_REGTYPE_RA:
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shift = 10;
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break;
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case AARCH64_INSN_REGTYPE_RM:
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shift = 16;
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break;
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default:
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pr_err("%s: unknown register type encoding %d\n", __func__,
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type);
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return 0;
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}
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return (insn >> shift) & GENMASK(4, 0);
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}
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static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
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u32 insn,
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enum aarch64_insn_register reg)
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{
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int shift;
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if (insn == AARCH64_BREAK_FAULT)
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return AARCH64_BREAK_FAULT;
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if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
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pr_err("%s: unknown register encoding %d\n", __func__, reg);
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return AARCH64_BREAK_FAULT;
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}
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switch (type) {
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case AARCH64_INSN_REGTYPE_RT:
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case AARCH64_INSN_REGTYPE_RD:
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shift = 0;
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break;
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case AARCH64_INSN_REGTYPE_RN:
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shift = 5;
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break;
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case AARCH64_INSN_REGTYPE_RT2:
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case AARCH64_INSN_REGTYPE_RA:
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shift = 10;
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break;
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case AARCH64_INSN_REGTYPE_RM:
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shift = 16;
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break;
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default:
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pr_err("%s: unknown register type encoding %d\n", __func__,
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type);
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return AARCH64_BREAK_FAULT;
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}
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insn &= ~(GENMASK(4, 0) << shift);
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insn |= reg << shift;
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return insn;
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}
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static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
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|
u32 insn)
|
|
{
|
|
u32 size;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_SIZE_8:
|
|
size = 0;
|
|
break;
|
|
case AARCH64_INSN_SIZE_16:
|
|
size = 1;
|
|
break;
|
|
case AARCH64_INSN_SIZE_32:
|
|
size = 2;
|
|
break;
|
|
case AARCH64_INSN_SIZE_64:
|
|
size = 3;
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown size encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
insn &= ~GENMASK(31, 30);
|
|
insn |= size << 30;
|
|
|
|
return insn;
|
|
}
|
|
|
|
static inline long branch_imm_common(unsigned long pc, unsigned long addr,
|
|
long range)
|
|
{
|
|
long offset;
|
|
|
|
if ((pc & 0x3) || (addr & 0x3)) {
|
|
pr_err("%s: A64 instructions must be word aligned\n", __func__);
|
|
return range;
|
|
}
|
|
|
|
offset = ((long)addr - (long)pc);
|
|
|
|
if (offset < -range || offset >= range) {
|
|
pr_err("%s: offset out of range\n", __func__);
|
|
return range;
|
|
}
|
|
|
|
return offset;
|
|
}
|
|
|
|
u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
|
|
enum aarch64_insn_branch_type type)
|
|
{
|
|
u32 insn;
|
|
long offset;
|
|
|
|
/*
|
|
* B/BL support [-128M, 128M) offset
|
|
* ARM64 virtual address arrangement guarantees all kernel and module
|
|
* texts are within +/-128M.
|
|
*/
|
|
offset = branch_imm_common(pc, addr, SZ_128M);
|
|
if (offset >= SZ_128M)
|
|
return AARCH64_BREAK_FAULT;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_BRANCH_LINK:
|
|
insn = aarch64_insn_get_bl_value();
|
|
break;
|
|
case AARCH64_INSN_BRANCH_NOLINK:
|
|
insn = aarch64_insn_get_b_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown branch encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
|
|
offset >> 2);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
|
|
enum aarch64_insn_register reg,
|
|
enum aarch64_insn_variant variant,
|
|
enum aarch64_insn_branch_type type)
|
|
{
|
|
u32 insn;
|
|
long offset;
|
|
|
|
offset = branch_imm_common(pc, addr, SZ_1M);
|
|
if (offset >= SZ_1M)
|
|
return AARCH64_BREAK_FAULT;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_BRANCH_COMP_ZERO:
|
|
insn = aarch64_insn_get_cbz_value();
|
|
break;
|
|
case AARCH64_INSN_BRANCH_COMP_NONZERO:
|
|
insn = aarch64_insn_get_cbnz_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown branch encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
switch (variant) {
|
|
case AARCH64_INSN_VARIANT_32BIT:
|
|
break;
|
|
case AARCH64_INSN_VARIANT_64BIT:
|
|
insn |= AARCH64_INSN_SF_BIT;
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
|
|
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
|
|
offset >> 2);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
|
|
enum aarch64_insn_condition cond)
|
|
{
|
|
u32 insn;
|
|
long offset;
|
|
|
|
offset = branch_imm_common(pc, addr, SZ_1M);
|
|
|
|
insn = aarch64_insn_get_bcond_value();
|
|
|
|
if (cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL) {
|
|
pr_err("%s: unknown condition encoding %d\n", __func__, cond);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
insn |= cond;
|
|
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
|
|
offset >> 2);
|
|
}
|
|
|
|
u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
|
|
{
|
|
return aarch64_insn_get_hint_value() | op;
|
|
}
|
|
|
|
u32 __kprobes aarch64_insn_gen_nop(void)
|
|
{
|
|
return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
|
|
enum aarch64_insn_branch_type type)
|
|
{
|
|
u32 insn;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_BRANCH_NOLINK:
|
|
insn = aarch64_insn_get_br_value();
|
|
break;
|
|
case AARCH64_INSN_BRANCH_LINK:
|
|
insn = aarch64_insn_get_blr_value();
|
|
break;
|
|
case AARCH64_INSN_BRANCH_RETURN:
|
|
insn = aarch64_insn_get_ret_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown branch encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
|
|
enum aarch64_insn_register base,
|
|
enum aarch64_insn_register offset,
|
|
enum aarch64_insn_size_type size,
|
|
enum aarch64_insn_ldst_type type)
|
|
{
|
|
u32 insn;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
|
|
insn = aarch64_insn_get_ldr_reg_value();
|
|
break;
|
|
case AARCH64_INSN_LDST_STORE_REG_OFFSET:
|
|
insn = aarch64_insn_get_str_reg_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown load/store encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
insn = aarch64_insn_encode_ldst_size(size, insn);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
|
|
base);
|
|
|
|
return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
|
|
offset);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
|
|
enum aarch64_insn_register reg2,
|
|
enum aarch64_insn_register base,
|
|
int offset,
|
|
enum aarch64_insn_variant variant,
|
|
enum aarch64_insn_ldst_type type)
|
|
{
|
|
u32 insn;
|
|
int shift;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
|
|
insn = aarch64_insn_get_ldp_pre_value();
|
|
break;
|
|
case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
|
|
insn = aarch64_insn_get_stp_pre_value();
|
|
break;
|
|
case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
|
|
insn = aarch64_insn_get_ldp_post_value();
|
|
break;
|
|
case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
|
|
insn = aarch64_insn_get_stp_post_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown load/store encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
switch (variant) {
|
|
case AARCH64_INSN_VARIANT_32BIT:
|
|
if ((offset & 0x3) || (offset < -256) || (offset > 252)) {
|
|
pr_err("%s: offset must be multiples of 4 in the range of [-256, 252] %d\n",
|
|
__func__, offset);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
shift = 2;
|
|
break;
|
|
case AARCH64_INSN_VARIANT_64BIT:
|
|
if ((offset & 0x7) || (offset < -512) || (offset > 504)) {
|
|
pr_err("%s: offset must be multiples of 8 in the range of [-512, 504] %d\n",
|
|
__func__, offset);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
shift = 3;
|
|
insn |= AARCH64_INSN_SF_BIT;
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
|
|
reg1);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
|
|
reg2);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
|
|
base);
|
|
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
|
|
offset >> shift);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
|
|
enum aarch64_insn_register src,
|
|
int imm, enum aarch64_insn_variant variant,
|
|
enum aarch64_insn_adsb_type type)
|
|
{
|
|
u32 insn;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_ADSB_ADD:
|
|
insn = aarch64_insn_get_add_imm_value();
|
|
break;
|
|
case AARCH64_INSN_ADSB_SUB:
|
|
insn = aarch64_insn_get_sub_imm_value();
|
|
break;
|
|
case AARCH64_INSN_ADSB_ADD_SETFLAGS:
|
|
insn = aarch64_insn_get_adds_imm_value();
|
|
break;
|
|
case AARCH64_INSN_ADSB_SUB_SETFLAGS:
|
|
insn = aarch64_insn_get_subs_imm_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
switch (variant) {
|
|
case AARCH64_INSN_VARIANT_32BIT:
|
|
break;
|
|
case AARCH64_INSN_VARIANT_64BIT:
|
|
insn |= AARCH64_INSN_SF_BIT;
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
if (imm & ~(SZ_4K - 1)) {
|
|
pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
|
|
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
|
|
enum aarch64_insn_register src,
|
|
int immr, int imms,
|
|
enum aarch64_insn_variant variant,
|
|
enum aarch64_insn_bitfield_type type)
|
|
{
|
|
u32 insn;
|
|
u32 mask;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_BITFIELD_MOVE:
|
|
insn = aarch64_insn_get_bfm_value();
|
|
break;
|
|
case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
|
|
insn = aarch64_insn_get_ubfm_value();
|
|
break;
|
|
case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
|
|
insn = aarch64_insn_get_sbfm_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown bitfield encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
switch (variant) {
|
|
case AARCH64_INSN_VARIANT_32BIT:
|
|
mask = GENMASK(4, 0);
|
|
break;
|
|
case AARCH64_INSN_VARIANT_64BIT:
|
|
insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
|
|
mask = GENMASK(5, 0);
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
if (immr & ~mask) {
|
|
pr_err("%s: invalid immr encoding %d\n", __func__, immr);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
if (imms & ~mask) {
|
|
pr_err("%s: invalid imms encoding %d\n", __func__, imms);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
|
|
|
|
insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
|
|
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
|
|
int imm, int shift,
|
|
enum aarch64_insn_variant variant,
|
|
enum aarch64_insn_movewide_type type)
|
|
{
|
|
u32 insn;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_MOVEWIDE_ZERO:
|
|
insn = aarch64_insn_get_movz_value();
|
|
break;
|
|
case AARCH64_INSN_MOVEWIDE_KEEP:
|
|
insn = aarch64_insn_get_movk_value();
|
|
break;
|
|
case AARCH64_INSN_MOVEWIDE_INVERSE:
|
|
insn = aarch64_insn_get_movn_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown movewide encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
if (imm & ~(SZ_64K - 1)) {
|
|
pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
switch (variant) {
|
|
case AARCH64_INSN_VARIANT_32BIT:
|
|
if (shift != 0 && shift != 16) {
|
|
pr_err("%s: invalid shift encoding %d\n", __func__,
|
|
shift);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
break;
|
|
case AARCH64_INSN_VARIANT_64BIT:
|
|
insn |= AARCH64_INSN_SF_BIT;
|
|
if (shift != 0 && shift != 16 && shift != 32 && shift != 48) {
|
|
pr_err("%s: invalid shift encoding %d\n", __func__,
|
|
shift);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
insn |= (shift >> 4) << 21;
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
|
|
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
|
|
enum aarch64_insn_register src,
|
|
enum aarch64_insn_register reg,
|
|
int shift,
|
|
enum aarch64_insn_variant variant,
|
|
enum aarch64_insn_adsb_type type)
|
|
{
|
|
u32 insn;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_ADSB_ADD:
|
|
insn = aarch64_insn_get_add_value();
|
|
break;
|
|
case AARCH64_INSN_ADSB_SUB:
|
|
insn = aarch64_insn_get_sub_value();
|
|
break;
|
|
case AARCH64_INSN_ADSB_ADD_SETFLAGS:
|
|
insn = aarch64_insn_get_adds_value();
|
|
break;
|
|
case AARCH64_INSN_ADSB_SUB_SETFLAGS:
|
|
insn = aarch64_insn_get_subs_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
switch (variant) {
|
|
case AARCH64_INSN_VARIANT_32BIT:
|
|
if (shift & ~(SZ_32 - 1)) {
|
|
pr_err("%s: invalid shift encoding %d\n", __func__,
|
|
shift);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
break;
|
|
case AARCH64_INSN_VARIANT_64BIT:
|
|
insn |= AARCH64_INSN_SF_BIT;
|
|
if (shift & ~(SZ_64 - 1)) {
|
|
pr_err("%s: invalid shift encoding %d\n", __func__,
|
|
shift);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
|
|
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
|
|
enum aarch64_insn_register src,
|
|
enum aarch64_insn_variant variant,
|
|
enum aarch64_insn_data1_type type)
|
|
{
|
|
u32 insn;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_DATA1_REVERSE_16:
|
|
insn = aarch64_insn_get_rev16_value();
|
|
break;
|
|
case AARCH64_INSN_DATA1_REVERSE_32:
|
|
insn = aarch64_insn_get_rev32_value();
|
|
break;
|
|
case AARCH64_INSN_DATA1_REVERSE_64:
|
|
if (variant != AARCH64_INSN_VARIANT_64BIT) {
|
|
pr_err("%s: invalid variant for reverse64 %d\n",
|
|
__func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
insn = aarch64_insn_get_rev64_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown data1 encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
switch (variant) {
|
|
case AARCH64_INSN_VARIANT_32BIT:
|
|
break;
|
|
case AARCH64_INSN_VARIANT_64BIT:
|
|
insn |= AARCH64_INSN_SF_BIT;
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
|
|
|
|
return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
|
|
enum aarch64_insn_register src,
|
|
enum aarch64_insn_register reg,
|
|
enum aarch64_insn_variant variant,
|
|
enum aarch64_insn_data2_type type)
|
|
{
|
|
u32 insn;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_DATA2_UDIV:
|
|
insn = aarch64_insn_get_udiv_value();
|
|
break;
|
|
case AARCH64_INSN_DATA2_SDIV:
|
|
insn = aarch64_insn_get_sdiv_value();
|
|
break;
|
|
case AARCH64_INSN_DATA2_LSLV:
|
|
insn = aarch64_insn_get_lslv_value();
|
|
break;
|
|
case AARCH64_INSN_DATA2_LSRV:
|
|
insn = aarch64_insn_get_lsrv_value();
|
|
break;
|
|
case AARCH64_INSN_DATA2_ASRV:
|
|
insn = aarch64_insn_get_asrv_value();
|
|
break;
|
|
case AARCH64_INSN_DATA2_RORV:
|
|
insn = aarch64_insn_get_rorv_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown data2 encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
switch (variant) {
|
|
case AARCH64_INSN_VARIANT_32BIT:
|
|
break;
|
|
case AARCH64_INSN_VARIANT_64BIT:
|
|
insn |= AARCH64_INSN_SF_BIT;
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
|
|
|
|
return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
|
|
enum aarch64_insn_register src,
|
|
enum aarch64_insn_register reg1,
|
|
enum aarch64_insn_register reg2,
|
|
enum aarch64_insn_variant variant,
|
|
enum aarch64_insn_data3_type type)
|
|
{
|
|
u32 insn;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_DATA3_MADD:
|
|
insn = aarch64_insn_get_madd_value();
|
|
break;
|
|
case AARCH64_INSN_DATA3_MSUB:
|
|
insn = aarch64_insn_get_msub_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown data3 encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
switch (variant) {
|
|
case AARCH64_INSN_VARIANT_32BIT:
|
|
break;
|
|
case AARCH64_INSN_VARIANT_64BIT:
|
|
insn |= AARCH64_INSN_SF_BIT;
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
|
|
reg1);
|
|
|
|
return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
|
|
reg2);
|
|
}
|
|
|
|
u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
|
|
enum aarch64_insn_register src,
|
|
enum aarch64_insn_register reg,
|
|
int shift,
|
|
enum aarch64_insn_variant variant,
|
|
enum aarch64_insn_logic_type type)
|
|
{
|
|
u32 insn;
|
|
|
|
switch (type) {
|
|
case AARCH64_INSN_LOGIC_AND:
|
|
insn = aarch64_insn_get_and_value();
|
|
break;
|
|
case AARCH64_INSN_LOGIC_BIC:
|
|
insn = aarch64_insn_get_bic_value();
|
|
break;
|
|
case AARCH64_INSN_LOGIC_ORR:
|
|
insn = aarch64_insn_get_orr_value();
|
|
break;
|
|
case AARCH64_INSN_LOGIC_ORN:
|
|
insn = aarch64_insn_get_orn_value();
|
|
break;
|
|
case AARCH64_INSN_LOGIC_EOR:
|
|
insn = aarch64_insn_get_eor_value();
|
|
break;
|
|
case AARCH64_INSN_LOGIC_EON:
|
|
insn = aarch64_insn_get_eon_value();
|
|
break;
|
|
case AARCH64_INSN_LOGIC_AND_SETFLAGS:
|
|
insn = aarch64_insn_get_ands_value();
|
|
break;
|
|
case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
|
|
insn = aarch64_insn_get_bics_value();
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown logical encoding %d\n", __func__, type);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
switch (variant) {
|
|
case AARCH64_INSN_VARIANT_32BIT:
|
|
if (shift & ~(SZ_32 - 1)) {
|
|
pr_err("%s: invalid shift encoding %d\n", __func__,
|
|
shift);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
break;
|
|
case AARCH64_INSN_VARIANT_64BIT:
|
|
insn |= AARCH64_INSN_SF_BIT;
|
|
if (shift & ~(SZ_64 - 1)) {
|
|
pr_err("%s: invalid shift encoding %d\n", __func__,
|
|
shift);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
break;
|
|
default:
|
|
pr_err("%s: unknown variant encoding %d\n", __func__, variant);
|
|
return AARCH64_BREAK_FAULT;
|
|
}
|
|
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
|
|
|
|
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
|
|
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
|
|
}
|
|
|
|
/*
|
|
* Decode the imm field of a branch, and return the byte offset as a
|
|
* signed value (so it can be used when computing a new branch
|
|
* target).
|
|
*/
|
|
s32 aarch64_get_branch_offset(u32 insn)
|
|
{
|
|
s32 imm;
|
|
|
|
if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) {
|
|
imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn);
|
|
return (imm << 6) >> 4;
|
|
}
|
|
|
|
if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
|
|
aarch64_insn_is_bcond(insn)) {
|
|
imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn);
|
|
return (imm << 13) >> 11;
|
|
}
|
|
|
|
if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) {
|
|
imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn);
|
|
return (imm << 18) >> 16;
|
|
}
|
|
|
|
/* Unhandled instruction */
|
|
BUG();
|
|
}
|
|
|
|
/*
|
|
* Encode the displacement of a branch in the imm field and return the
|
|
* updated instruction.
|
|
*/
|
|
u32 aarch64_set_branch_offset(u32 insn, s32 offset)
|
|
{
|
|
if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn))
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
|
|
offset >> 2);
|
|
|
|
if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
|
|
aarch64_insn_is_bcond(insn))
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
|
|
offset >> 2);
|
|
|
|
if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn))
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_14, insn,
|
|
offset >> 2);
|
|
|
|
/* Unhandled instruction */
|
|
BUG();
|
|
}
|
|
|
|
s32 aarch64_insn_adrp_get_offset(u32 insn)
|
|
{
|
|
BUG_ON(!aarch64_insn_is_adrp(insn));
|
|
return aarch64_insn_decode_immediate(AARCH64_INSN_IMM_ADR, insn) << 12;
|
|
}
|
|
|
|
u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
|
|
{
|
|
BUG_ON(!aarch64_insn_is_adrp(insn));
|
|
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn,
|
|
offset >> 12);
|
|
}
|
|
|
|
/*
|
|
* Extract the Op/CR data from a msr/mrs instruction.
|
|
*/
|
|
u32 aarch64_insn_extract_system_reg(u32 insn)
|
|
{
|
|
return (insn & 0x1FFFE0) >> 5;
|
|
}
|
|
|
|
bool aarch32_insn_is_wide(u32 insn)
|
|
{
|
|
return insn >= 0xe800;
|
|
}
|
|
|
|
/*
|
|
* Macros/defines for extracting register numbers from instruction.
|
|
*/
|
|
u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
|
|
{
|
|
return (insn & (0xf << offset)) >> offset;
|
|
}
|
|
|
|
#define OPC2_MASK 0x7
|
|
#define OPC2_OFFSET 5
|
|
u32 aarch32_insn_mcr_extract_opc2(u32 insn)
|
|
{
|
|
return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
|
|
}
|
|
|
|
#define CRM_MASK 0xf
|
|
u32 aarch32_insn_mcr_extract_crm(u32 insn)
|
|
{
|
|
return insn & CRM_MASK;
|
|
}
|
|
|
|
static bool __kprobes __check_eq(unsigned long pstate)
|
|
{
|
|
return (pstate & PSR_Z_BIT) != 0;
|
|
}
|
|
|
|
static bool __kprobes __check_ne(unsigned long pstate)
|
|
{
|
|
return (pstate & PSR_Z_BIT) == 0;
|
|
}
|
|
|
|
static bool __kprobes __check_cs(unsigned long pstate)
|
|
{
|
|
return (pstate & PSR_C_BIT) != 0;
|
|
}
|
|
|
|
static bool __kprobes __check_cc(unsigned long pstate)
|
|
{
|
|
return (pstate & PSR_C_BIT) == 0;
|
|
}
|
|
|
|
static bool __kprobes __check_mi(unsigned long pstate)
|
|
{
|
|
return (pstate & PSR_N_BIT) != 0;
|
|
}
|
|
|
|
static bool __kprobes __check_pl(unsigned long pstate)
|
|
{
|
|
return (pstate & PSR_N_BIT) == 0;
|
|
}
|
|
|
|
static bool __kprobes __check_vs(unsigned long pstate)
|
|
{
|
|
return (pstate & PSR_V_BIT) != 0;
|
|
}
|
|
|
|
static bool __kprobes __check_vc(unsigned long pstate)
|
|
{
|
|
return (pstate & PSR_V_BIT) == 0;
|
|
}
|
|
|
|
static bool __kprobes __check_hi(unsigned long pstate)
|
|
{
|
|
pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
|
|
return (pstate & PSR_C_BIT) != 0;
|
|
}
|
|
|
|
static bool __kprobes __check_ls(unsigned long pstate)
|
|
{
|
|
pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
|
|
return (pstate & PSR_C_BIT) == 0;
|
|
}
|
|
|
|
static bool __kprobes __check_ge(unsigned long pstate)
|
|
{
|
|
pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
|
|
return (pstate & PSR_N_BIT) == 0;
|
|
}
|
|
|
|
static bool __kprobes __check_lt(unsigned long pstate)
|
|
{
|
|
pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
|
|
return (pstate & PSR_N_BIT) != 0;
|
|
}
|
|
|
|
static bool __kprobes __check_gt(unsigned long pstate)
|
|
{
|
|
/*PSR_N_BIT ^= PSR_V_BIT */
|
|
unsigned long temp = pstate ^ (pstate << 3);
|
|
|
|
temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
|
|
return (temp & PSR_N_BIT) == 0;
|
|
}
|
|
|
|
static bool __kprobes __check_le(unsigned long pstate)
|
|
{
|
|
/*PSR_N_BIT ^= PSR_V_BIT */
|
|
unsigned long temp = pstate ^ (pstate << 3);
|
|
|
|
temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
|
|
return (temp & PSR_N_BIT) != 0;
|
|
}
|
|
|
|
static bool __kprobes __check_al(unsigned long pstate)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
/*
|
|
* Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
|
|
* it behaves identically to 0b1110 ("al").
|
|
*/
|
|
pstate_check_t * const aarch32_opcode_cond_checks[16] = {
|
|
__check_eq, __check_ne, __check_cs, __check_cc,
|
|
__check_mi, __check_pl, __check_vs, __check_vc,
|
|
__check_hi, __check_ls, __check_ge, __check_lt,
|
|
__check_gt, __check_le, __check_al, __check_al
|
|
};
|