mirror of https://gitee.com/openkylin/linux.git
171 lines
4.1 KiB
C
171 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for HiSilicon SoCs
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*
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* Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
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*
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* Authors: Zhou Wang <wangzhou1@hisilicon.com>
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* Dacai Zhu <zhudacai@hisilicon.com>
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* Gabriele Paoloni <gabriele.paoloni@huawei.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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#include "../../pci.h"
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#if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
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static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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int dev = PCI_SLOT(devfn);
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if (bus->number == cfg->busr.start) {
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/* access only one slot on each root port */
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if (dev > 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return pci_generic_config_read32(bus, devfn, where,
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size, val);
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}
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return pci_generic_config_read(bus, devfn, where, size, val);
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}
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static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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int dev = PCI_SLOT(devfn);
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if (bus->number == cfg->busr.start) {
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/* access only one slot on each root port */
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if (dev > 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return pci_generic_config_write32(bus, devfn, where,
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size, val);
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}
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return pci_generic_config_write(bus, devfn, where, size, val);
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}
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static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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struct pci_config_window *cfg = bus->sysdata;
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void __iomem *reg_base = cfg->priv;
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if (bus->number == cfg->busr.start)
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return reg_base + where;
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else
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return pci_ecam_map_bus(bus, devfn, where);
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}
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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static int hisi_pcie_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct acpi_device *adev = to_acpi_device(dev);
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struct acpi_pci_root *root = acpi_driver_data(adev);
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struct resource *res;
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void __iomem *reg_base;
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int ret;
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/*
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* Retrieve RC base and size from a HISI0081 device with _UID
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* matching our segment.
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*/
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res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
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if (!res)
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return -ENOMEM;
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ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
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if (ret) {
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dev_err(dev, "can't get rc base address\n");
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return -ENOMEM;
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}
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reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
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if (!reg_base)
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return -ENOMEM;
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cfg->priv = reg_base;
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return 0;
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}
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const struct pci_ecam_ops hisi_pcie_ops = {
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.bus_shift = 20,
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.init = hisi_pcie_init,
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.pci_ops = {
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.map_bus = hisi_pcie_map_bus,
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.read = hisi_pcie_rd_conf,
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.write = hisi_pcie_wr_conf,
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}
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};
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#endif
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#ifdef CONFIG_PCI_HISI
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static int hisi_pcie_platform_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *res;
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void __iomem *reg_base;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res) {
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dev_err(dev, "missing \"reg[1]\"property\n");
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return -EINVAL;
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}
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reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
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if (!reg_base)
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return -ENOMEM;
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cfg->priv = reg_base;
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return 0;
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}
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static const struct pci_ecam_ops hisi_pcie_platform_ops = {
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.bus_shift = 20,
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.init = hisi_pcie_platform_init,
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.pci_ops = {
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.map_bus = hisi_pcie_map_bus,
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.read = hisi_pcie_rd_conf,
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.write = hisi_pcie_wr_conf,
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}
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};
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static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
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{
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.compatible = "hisilicon,hip06-pcie-ecam",
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.data = &hisi_pcie_platform_ops,
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},
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{
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.compatible = "hisilicon,hip07-pcie-ecam",
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.data = &hisi_pcie_platform_ops,
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},
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{},
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};
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static struct platform_driver hisi_pcie_almost_ecam_driver = {
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.probe = pci_host_common_probe,
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.driver = {
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.name = "hisi-pcie-almost-ecam",
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.of_match_table = hisi_pcie_almost_ecam_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(hisi_pcie_almost_ecam_driver);
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#endif
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#endif
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