mirror of https://gitee.com/openkylin/linux.git
177 lines
5.2 KiB
C
177 lines
5.2 KiB
C
/*
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* r8a7779 clock framework support
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/common.h>
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#define FRQMR 0xffc80014
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#define MSTPCR0 0xffc80030
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#define MSTPCR1 0xffc80034
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#define MSTPCR3 0xffc8003c
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#define MSTPSR1 0xffc80044
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#define MSTPSR4 0xffc80048
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#define MSTPSR6 0xffc8004c
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#define MSTPCR4 0xffc80050
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#define MSTPCR5 0xffc80054
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#define MSTPCR6 0xffc80058
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#define MSTPCR7 0xffc80040
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/* ioremap() through clock mapping mandatory to avoid
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* collision with ARM coherent DMA virtual memory range.
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*/
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static struct clk_mapping cpg_mapping = {
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.phys = 0xffc80000,
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.len = 0x80,
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};
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk plla_clk = {
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.rate = 1500000000,
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.mapping = &cpg_mapping,
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};
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static struct clk *main_clks[] = {
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&plla_clk,
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};
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static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
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static struct clk div4_clks[DIV4_NR] = {
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[DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
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0x0018, CLK_ENABLE_ON_INIT),
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[DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
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0x0700, CLK_ENABLE_ON_INIT),
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[DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
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0x0040, CLK_ENABLE_ON_INIT),
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[DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
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0x0010, CLK_ENABLE_ON_INIT),
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[DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
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0x0060, CLK_ENABLE_ON_INIT),
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[DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
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0x0300, CLK_ENABLE_ON_INIT),
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};
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enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
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MSTP016, MSTP015, MSTP014,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
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[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
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[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
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[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */
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[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */
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[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */
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[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
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[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
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[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
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};
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static unsigned long mul4_recalc(struct clk *clk)
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{
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return clk->parent->rate * 4;
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}
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static struct clk_ops mul4_clk_ops = {
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.recalc = mul4_recalc,
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};
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struct clk clkz_clk = {
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.ops = &mul4_clk_ops,
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.parent = &div4_clks[DIV4_S],
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};
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struct clk clkzs_clk = {
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/* clks x 4 / 4 = clks */
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.parent = &div4_clks[DIV4_S],
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};
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static struct clk *late_main_clks[] = {
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&clkz_clk,
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&clkzs_clk,
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("plla_clk", &plla_clk),
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CLKDEV_CON_ID("clkz_clk", &clkz_clk),
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CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
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CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]),
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CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]),
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CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]),
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CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]),
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CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
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CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
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};
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void __init r8a7779_clock_init(void)
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{
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int k, ret = 0;
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
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ret = clk_register(late_main_clks[k]);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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clk_init();
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else
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panic("failed to setup r8a7779 clocks\n");
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}
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