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95 lines
2.9 KiB
Plaintext
95 lines
2.9 KiB
Plaintext
* Samsung Exynos 5440 PCIe interface
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: "samsung,exynos5440-pcie"
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- reg: base addresses and lengths of the PCIe controller,
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the PHY controller, additional register for the PHY controller.
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(Registers for the PHY controller are DEPRECATED.
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Use the PHY framework.)
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- reg-names : First name should be set to "elbi".
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And use the "config" instead of getting the configuration address space
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from "ranges".
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NOTE: When using the "config" property, reg-names must be set.
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- interrupts: A list of interrupt outputs for level interrupt,
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pulse interrupt, special interrupt.
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- phys: From PHY binding. Phandle for the generic PHY.
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Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
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For other common properties, refer to
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Documentation/devicetree/bindings/pci/designware-pcie.txt
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Example:
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SoC-specific DT Entry:
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pcie@290000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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reg = <0x290000 0x1000
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0x270000 0x1000
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0x271000 0x40>;
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interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
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clocks = <&clock 28>, <&clock 27>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
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0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <4>;
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};
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pcie@2a0000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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reg = <0x2a0000 0x1000
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0x272000 0x1000
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0x271040 0x40>;
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interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
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clocks = <&clock 29>, <&clock 27>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
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0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <4>;
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};
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With using PHY framework:
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pcie_phy0: pcie-phy@270000 {
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...
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reg = <0x270000 0x1000>, <0x271000 0x40>;
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reg-names = "phy", "block";
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...
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};
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pcie@290000 {
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...
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reg = <0x290000 0x1000>, <0x40000000 0x1000>;
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reg-names = "elbi", "config";
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phys = <&pcie_phy0>;
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ranges = <0x81000000 0 0 0x60001000 0 0x00010000
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0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
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...
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};
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Board-specific DT Entry:
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pcie@290000 {
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reset-gpio = <&pin_ctrl 5 0>;
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};
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pcie@2a0000 {
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reset-gpio = <&pin_ctrl 22 0>;
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};
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