mirror of https://gitee.com/openkylin/linux.git
644 lines
14 KiB
C
644 lines
14 KiB
C
#include <linux/aer.h>
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#include <linux/delay.h>
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#include <linux/debugfs.h>
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#include <linux/firmware.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include "nitrox_dev.h"
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#include "nitrox_common.h"
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#include "nitrox_csr.h"
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#define CNN55XX_DEV_ID 0x12
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#define MAX_PF_QUEUES 64
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#define UCODE_HLEN 48
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#define SE_GROUP 0
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#define DRIVER_VERSION "1.0"
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#define FW_DIR "cavium/"
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/* SE microcode */
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#define SE_FW FW_DIR "cnn55xx_se.fw"
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static const char nitrox_driver_name[] = "CNN55XX";
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static LIST_HEAD(ndevlist);
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static DEFINE_MUTEX(devlist_lock);
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static unsigned int num_devices;
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/**
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* nitrox_pci_tbl - PCI Device ID Table
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*/
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static const struct pci_device_id nitrox_pci_tbl[] = {
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{PCI_VDEVICE(CAVIUM, CNN55XX_DEV_ID), 0},
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/* required last entry */
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{0, }
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};
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MODULE_DEVICE_TABLE(pci, nitrox_pci_tbl);
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static unsigned int qlen = DEFAULT_CMD_QLEN;
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module_param(qlen, uint, 0644);
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MODULE_PARM_DESC(qlen, "Command queue length - default 2048");
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/**
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* struct ucode - Firmware Header
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* @id: microcode ID
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* @version: firmware version
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* @code_size: code section size
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* @raz: alignment
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* @code: code section
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*/
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struct ucode {
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u8 id;
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char version[VERSION_LEN - 1];
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__be32 code_size;
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u8 raz[12];
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u64 code[0];
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};
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/**
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* write_to_ucd_unit - Write Firmware to NITROX UCD unit
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*/
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static void write_to_ucd_unit(struct nitrox_device *ndev,
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struct ucode *ucode)
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{
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u32 code_size = be32_to_cpu(ucode->code_size) * 2;
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u64 offset, data;
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int i = 0;
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/*
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* UCD structure
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*
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* -------------
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* | BLK 7 |
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* -------------
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* | BLK 6 |
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* -------------
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* | ... |
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* -------------
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* | BLK 0 |
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* -------------
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* Total of 8 blocks, each size 32KB
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*/
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/* set the block number */
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offset = UCD_UCODE_LOAD_BLOCK_NUM;
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nitrox_write_csr(ndev, offset, 0);
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code_size = roundup(code_size, 8);
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while (code_size) {
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data = ucode->code[i];
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/* write 8 bytes at a time */
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offset = UCD_UCODE_LOAD_IDX_DATAX(i);
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nitrox_write_csr(ndev, offset, data);
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code_size -= 8;
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i++;
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}
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/* put all SE cores in group 0 */
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offset = POM_GRP_EXECMASKX(SE_GROUP);
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nitrox_write_csr(ndev, offset, (~0ULL));
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for (i = 0; i < ndev->hw.se_cores; i++) {
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/*
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* write block number and firware length
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* bit:<2:0> block number
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* bit:3 is set SE uses 32KB microcode
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* bit:3 is clear SE uses 64KB microcode
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*/
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offset = UCD_SE_EID_UCODE_BLOCK_NUMX(i);
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nitrox_write_csr(ndev, offset, 0x8);
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}
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usleep_range(300, 400);
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}
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static int nitrox_load_fw(struct nitrox_device *ndev, const char *fw_name)
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{
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const struct firmware *fw;
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struct ucode *ucode;
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int ret;
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dev_info(DEV(ndev), "Loading firmware \"%s\"\n", fw_name);
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ret = request_firmware(&fw, fw_name, DEV(ndev));
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if (ret < 0) {
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dev_err(DEV(ndev), "failed to get firmware %s\n", fw_name);
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return ret;
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}
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ucode = (struct ucode *)fw->data;
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/* copy the firmware version */
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memcpy(ndev->hw.fw_name, ucode->version, (VERSION_LEN - 2));
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ndev->hw.fw_name[VERSION_LEN - 1] = '\0';
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write_to_ucd_unit(ndev, ucode);
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release_firmware(fw);
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set_bit(NITROX_UCODE_LOADED, &ndev->status);
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/* barrier to sync with other cpus */
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smp_mb__after_atomic();
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return 0;
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}
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/**
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* nitrox_add_to_devlist - add NITROX device to global device list
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* @ndev: NITROX device
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*/
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static int nitrox_add_to_devlist(struct nitrox_device *ndev)
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{
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struct nitrox_device *dev;
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int ret = 0;
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INIT_LIST_HEAD(&ndev->list);
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refcount_set(&ndev->refcnt, 1);
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mutex_lock(&devlist_lock);
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list_for_each_entry(dev, &ndevlist, list) {
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if (dev == ndev) {
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ret = -EEXIST;
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goto unlock;
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}
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}
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ndev->idx = num_devices++;
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list_add_tail(&ndev->list, &ndevlist);
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unlock:
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mutex_unlock(&devlist_lock);
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return ret;
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}
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/**
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* nitrox_remove_from_devlist - remove NITROX device from
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* global device list
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* @ndev: NITROX device
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*/
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static void nitrox_remove_from_devlist(struct nitrox_device *ndev)
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{
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mutex_lock(&devlist_lock);
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list_del(&ndev->list);
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num_devices--;
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mutex_unlock(&devlist_lock);
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}
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struct nitrox_device *nitrox_get_first_device(void)
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{
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struct nitrox_device *ndev = NULL;
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mutex_lock(&devlist_lock);
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list_for_each_entry(ndev, &ndevlist, list) {
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if (nitrox_ready(ndev))
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break;
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}
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mutex_unlock(&devlist_lock);
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if (!ndev)
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return NULL;
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refcount_inc(&ndev->refcnt);
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/* barrier to sync with other cpus */
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smp_mb__after_atomic();
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return ndev;
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}
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void nitrox_put_device(struct nitrox_device *ndev)
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{
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if (!ndev)
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return;
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refcount_dec(&ndev->refcnt);
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/* barrier to sync with other cpus */
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smp_mb__after_atomic();
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}
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static int nitrox_reset_device(struct pci_dev *pdev)
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{
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int pos = 0;
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pos = pci_save_state(pdev);
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if (pos) {
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dev_err(&pdev->dev, "Failed to save pci state\n");
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return -ENOMEM;
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}
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pos = pci_pcie_cap(pdev);
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if (!pos)
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return -ENOTTY;
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if (!pci_wait_for_pending_transaction(pdev))
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dev_err(&pdev->dev, "waiting for pending transaction\n");
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pcie_capability_set_word(pdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
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msleep(100);
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pci_restore_state(pdev);
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return 0;
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}
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static int nitrox_pf_sw_init(struct nitrox_device *ndev)
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{
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int err;
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err = nitrox_common_sw_init(ndev);
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if (err)
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return err;
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err = nitrox_pf_init_isr(ndev);
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if (err)
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nitrox_common_sw_cleanup(ndev);
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return err;
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}
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static void nitrox_pf_sw_cleanup(struct nitrox_device *ndev)
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{
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nitrox_pf_cleanup_isr(ndev);
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nitrox_common_sw_cleanup(ndev);
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}
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/**
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* nitrox_bist_check - Check NITORX BIST registers status
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* @ndev: NITROX device
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*/
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static int nitrox_bist_check(struct nitrox_device *ndev)
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{
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u64 value = 0;
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int i;
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for (i = 0; i < NR_CLUSTERS; i++) {
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value += nitrox_read_csr(ndev, EMU_BIST_STATUSX(i));
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value += nitrox_read_csr(ndev, EFL_CORE_BIST_REGX(i));
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}
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value += nitrox_read_csr(ndev, UCD_BIST_STATUS);
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value += nitrox_read_csr(ndev, NPS_CORE_BIST_REG);
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value += nitrox_read_csr(ndev, NPS_CORE_NPC_BIST_REG);
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value += nitrox_read_csr(ndev, NPS_PKT_SLC_BIST_REG);
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value += nitrox_read_csr(ndev, NPS_PKT_IN_BIST_REG);
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value += nitrox_read_csr(ndev, POM_BIST_REG);
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value += nitrox_read_csr(ndev, BMI_BIST_REG);
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value += nitrox_read_csr(ndev, EFL_TOP_BIST_STAT);
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value += nitrox_read_csr(ndev, BMO_BIST_REG);
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value += nitrox_read_csr(ndev, LBC_BIST_STATUS);
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value += nitrox_read_csr(ndev, PEM_BIST_STATUSX(0));
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if (value)
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return -EIO;
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return 0;
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}
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static void nitrox_get_hwinfo(struct nitrox_device *ndev)
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{
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union emu_fuse_map emu_fuse;
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u64 offset;
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int i;
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for (i = 0; i < NR_CLUSTERS; i++) {
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u8 dead_cores;
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offset = EMU_FUSE_MAPX(i);
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emu_fuse.value = nitrox_read_csr(ndev, offset);
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if (emu_fuse.s.valid) {
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dead_cores = hweight32(emu_fuse.s.ae_fuse);
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ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores;
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dead_cores = hweight16(emu_fuse.s.se_fuse);
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ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores;
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}
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}
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}
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static int nitrox_pf_hw_init(struct nitrox_device *ndev)
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{
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int err;
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err = nitrox_bist_check(ndev);
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if (err) {
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dev_err(&ndev->pdev->dev, "BIST check failed\n");
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return err;
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}
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/* get cores information */
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nitrox_get_hwinfo(ndev);
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nitrox_config_nps_unit(ndev);
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nitrox_config_pom_unit(ndev);
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nitrox_config_efl_unit(ndev);
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/* configure IO units */
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nitrox_config_bmi_unit(ndev);
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nitrox_config_bmo_unit(ndev);
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/* configure Local Buffer Cache */
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nitrox_config_lbc_unit(ndev);
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nitrox_config_rand_unit(ndev);
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/* load firmware on SE cores */
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err = nitrox_load_fw(ndev, SE_FW);
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if (err)
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return err;
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nitrox_config_emu_unit(ndev);
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return 0;
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}
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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static int registers_show(struct seq_file *s, void *v)
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{
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struct nitrox_device *ndev = s->private;
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u64 offset;
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/* NPS DMA stats */
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offset = NPS_STATS_PKT_DMA_RD_CNT;
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seq_printf(s, "NPS_STATS_PKT_DMA_RD_CNT 0x%016llx\n",
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nitrox_read_csr(ndev, offset));
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offset = NPS_STATS_PKT_DMA_WR_CNT;
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seq_printf(s, "NPS_STATS_PKT_DMA_WR_CNT 0x%016llx\n",
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nitrox_read_csr(ndev, offset));
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/* BMI/BMO stats */
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offset = BMI_NPS_PKT_CNT;
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seq_printf(s, "BMI_NPS_PKT_CNT 0x%016llx\n",
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nitrox_read_csr(ndev, offset));
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offset = BMO_NPS_SLC_PKT_CNT;
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seq_printf(s, "BMO_NPS_PKT_CNT 0x%016llx\n",
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nitrox_read_csr(ndev, offset));
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return 0;
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}
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static int registers_open(struct inode *inode, struct file *file)
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{
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return single_open(file, registers_show, inode->i_private);
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}
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static const struct file_operations register_fops = {
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.owner = THIS_MODULE,
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.open = registers_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int firmware_show(struct seq_file *s, void *v)
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{
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struct nitrox_device *ndev = s->private;
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seq_printf(s, "Version: %s\n", ndev->hw.fw_name);
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return 0;
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}
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static int firmware_open(struct inode *inode, struct file *file)
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{
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return single_open(file, firmware_show, inode->i_private);
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}
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static const struct file_operations firmware_fops = {
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.owner = THIS_MODULE,
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.open = firmware_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int nitrox_show(struct seq_file *s, void *v)
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{
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struct nitrox_device *ndev = s->private;
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seq_printf(s, "NITROX-5 [idx: %d]\n", ndev->idx);
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seq_printf(s, " Revision ID: 0x%0x\n", ndev->hw.revision_id);
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seq_printf(s, " Cores [AE: %u SE: %u]\n",
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ndev->hw.ae_cores, ndev->hw.se_cores);
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seq_printf(s, " Number of Queues: %u\n", ndev->nr_queues);
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seq_printf(s, " Queue length: %u\n", ndev->qlen);
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seq_printf(s, " Node: %u\n", ndev->node);
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return 0;
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}
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static int nitrox_open(struct inode *inode, struct file *file)
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{
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return single_open(file, nitrox_show, inode->i_private);
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}
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static const struct file_operations nitrox_fops = {
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.owner = THIS_MODULE,
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.open = nitrox_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static void nitrox_debugfs_exit(struct nitrox_device *ndev)
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{
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debugfs_remove_recursive(ndev->debugfs_dir);
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ndev->debugfs_dir = NULL;
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}
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static int nitrox_debugfs_init(struct nitrox_device *ndev)
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{
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struct dentry *dir, *f;
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dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
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if (!dir)
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return -ENOMEM;
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ndev->debugfs_dir = dir;
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f = debugfs_create_file("counters", 0400, dir, ndev, ®ister_fops);
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if (!f)
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goto err;
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f = debugfs_create_file("firmware", 0400, dir, ndev, &firmware_fops);
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if (!f)
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goto err;
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f = debugfs_create_file("nitrox", 0400, dir, ndev, &nitrox_fops);
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if (!f)
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goto err;
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return 0;
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err:
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nitrox_debugfs_exit(ndev);
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return -ENODEV;
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}
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#else
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static int nitrox_debugfs_init(struct nitrox_device *ndev)
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{
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return 0;
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}
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static void nitrox_debugfs_exit(struct nitrox_device *ndev)
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{
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}
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#endif
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/**
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* nitrox_probe - NITROX Initialization function.
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* @pdev: PCI device information struct
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* @id: entry in nitrox_pci_tbl
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*
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* Return: 0, if the driver is bound to the device, or
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* a negative error if there is failure.
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*/
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static int nitrox_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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struct nitrox_device *ndev;
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int err;
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dev_info_once(&pdev->dev, "%s driver version %s\n",
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nitrox_driver_name, DRIVER_VERSION);
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err = pci_enable_device_mem(pdev);
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if (err)
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return err;
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/* do FLR */
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err = nitrox_reset_device(pdev);
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if (err) {
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dev_err(&pdev->dev, "FLR failed\n");
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pci_disable_device(pdev);
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return err;
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}
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if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
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dev_dbg(&pdev->dev, "DMA to 64-BIT address\n");
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} else {
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err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
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if (err) {
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dev_err(&pdev->dev, "DMA configuration failed\n");
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pci_disable_device(pdev);
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return err;
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}
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}
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err = pci_request_mem_regions(pdev, nitrox_driver_name);
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if (err) {
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pci_disable_device(pdev);
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return err;
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}
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pci_set_master(pdev);
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ndev = kzalloc(sizeof(*ndev), GFP_KERNEL);
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if (!ndev) {
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err = -ENOMEM;
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goto ndev_fail;
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}
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|
pci_set_drvdata(pdev, ndev);
|
|
ndev->pdev = pdev;
|
|
|
|
/* add to device list */
|
|
nitrox_add_to_devlist(ndev);
|
|
|
|
ndev->hw.vendor_id = pdev->vendor;
|
|
ndev->hw.device_id = pdev->device;
|
|
ndev->hw.revision_id = pdev->revision;
|
|
/* command timeout in jiffies */
|
|
ndev->timeout = msecs_to_jiffies(CMD_TIMEOUT);
|
|
ndev->node = dev_to_node(&pdev->dev);
|
|
if (ndev->node == NUMA_NO_NODE)
|
|
ndev->node = 0;
|
|
|
|
ndev->bar_addr = ioremap(pci_resource_start(pdev, 0),
|
|
pci_resource_len(pdev, 0));
|
|
if (!ndev->bar_addr) {
|
|
err = -EIO;
|
|
goto ioremap_err;
|
|
}
|
|
/* allocate command queus based on cpus, max queues are 64 */
|
|
ndev->nr_queues = min_t(u32, MAX_PF_QUEUES, num_online_cpus());
|
|
ndev->qlen = qlen;
|
|
|
|
err = nitrox_pf_sw_init(ndev);
|
|
if (err)
|
|
goto ioremap_err;
|
|
|
|
err = nitrox_pf_hw_init(ndev);
|
|
if (err)
|
|
goto pf_hw_fail;
|
|
|
|
err = nitrox_debugfs_init(ndev);
|
|
if (err)
|
|
goto pf_hw_fail;
|
|
|
|
set_bit(NITROX_READY, &ndev->status);
|
|
/* barrier to sync with other cpus */
|
|
smp_mb__after_atomic();
|
|
|
|
err = nitrox_crypto_register();
|
|
if (err)
|
|
goto crypto_fail;
|
|
|
|
return 0;
|
|
|
|
crypto_fail:
|
|
nitrox_debugfs_exit(ndev);
|
|
clear_bit(NITROX_READY, &ndev->status);
|
|
/* barrier to sync with other cpus */
|
|
smp_mb__after_atomic();
|
|
pf_hw_fail:
|
|
nitrox_pf_sw_cleanup(ndev);
|
|
ioremap_err:
|
|
nitrox_remove_from_devlist(ndev);
|
|
kfree(ndev);
|
|
pci_set_drvdata(pdev, NULL);
|
|
ndev_fail:
|
|
pci_release_mem_regions(pdev);
|
|
pci_disable_device(pdev);
|
|
return err;
|
|
}
|
|
|
|
/**
|
|
* nitrox_remove - Unbind the driver from the device.
|
|
* @pdev: PCI device information struct
|
|
*/
|
|
static void nitrox_remove(struct pci_dev *pdev)
|
|
{
|
|
struct nitrox_device *ndev = pci_get_drvdata(pdev);
|
|
|
|
if (!ndev)
|
|
return;
|
|
|
|
if (!refcount_dec_and_test(&ndev->refcnt)) {
|
|
dev_err(DEV(ndev), "Device refcnt not zero (%d)\n",
|
|
refcount_read(&ndev->refcnt));
|
|
return;
|
|
}
|
|
|
|
dev_info(DEV(ndev), "Removing Device %x:%x\n",
|
|
ndev->hw.vendor_id, ndev->hw.device_id);
|
|
|
|
clear_bit(NITROX_READY, &ndev->status);
|
|
/* barrier to sync with other cpus */
|
|
smp_mb__after_atomic();
|
|
|
|
nitrox_remove_from_devlist(ndev);
|
|
nitrox_crypto_unregister();
|
|
nitrox_debugfs_exit(ndev);
|
|
nitrox_pf_sw_cleanup(ndev);
|
|
|
|
iounmap(ndev->bar_addr);
|
|
kfree(ndev);
|
|
|
|
pci_set_drvdata(pdev, NULL);
|
|
pci_release_mem_regions(pdev);
|
|
pci_disable_device(pdev);
|
|
}
|
|
|
|
static void nitrox_shutdown(struct pci_dev *pdev)
|
|
{
|
|
pci_set_drvdata(pdev, NULL);
|
|
pci_release_mem_regions(pdev);
|
|
pci_disable_device(pdev);
|
|
}
|
|
|
|
static struct pci_driver nitrox_driver = {
|
|
.name = nitrox_driver_name,
|
|
.id_table = nitrox_pci_tbl,
|
|
.probe = nitrox_probe,
|
|
.remove = nitrox_remove,
|
|
.shutdown = nitrox_shutdown,
|
|
};
|
|
|
|
module_pci_driver(nitrox_driver);
|
|
|
|
MODULE_AUTHOR("Srikanth Jampala <Jampala.Srikanth@cavium.com>");
|
|
MODULE_DESCRIPTION("Cavium CNN55XX PF Driver" DRIVER_VERSION " ");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_VERSION(DRIVER_VERSION);
|
|
MODULE_FIRMWARE(SE_FW);
|