linux/arch/x86/events/intel
Jacek Tomaka 16160c1946 perf/x86/intel: Add support/quirk for the MISPREDICT bit on Knights Landing CPUs
Problem: perf did not show branch predicted/mispredicted bit in brstack.

Output of perf -F brstack for profile collected

Before:

 0x4fdbcd/0x4fdc03/-/-/-/0
 0x45f4c1/0x4fdba0/-/-/-/0
 0x45f544/0x45f4bb/-/-/-/0
 0x45f555/0x45f53c/-/-/-/0
 0x7f66901cc24b/0x45f555/-/-/-/0
 0x7f66901cc22e/0x7f66901cc23d/-/-/-/0
 0x7f66901cc1ff/0x7f66901cc20f/-/-/-/0
 0x7f66901cc1e8/0x7f66901cc1fc/-/-/-/0

After:

 0x4fdbcd/0x4fdc03/P/-/-/0
 0x45f4c1/0x4fdba0/P/-/-/0
 0x45f544/0x45f4bb/P/-/-/0
 0x45f555/0x45f53c/P/-/-/0
 0x7f66901cc24b/0x45f555/P/-/-/0
 0x7f66901cc22e/0x7f66901cc23d/P/-/-/0
 0x7f66901cc1ff/0x7f66901cc20f/P/-/-/0
 0x7f66901cc1e8/0x7f66901cc1fc/P/-/-/0

Cause:

As mentioned in Software Development Manual vol 3, 17.4.8.1,
IA32_PERF_CAPABILITIES[5:0] indicates the format of the address that is
stored in the LBR stack. Knights Landing reports 1 (LBR_FORMAT_LIP) as
its format. Despite that, registers containing FROM address of the branch,
do have MISPREDICT bit but because of the format indicated in
IA32_PERF_CAPABILITIES[5:0], LBR did not read MISPREDICT bit.

Solution:

Teach LBR about above Knights Landing quirk and make it read MISPREDICT bit.

Signed-off-by: Jacek Tomaka <jacek.tomaka@poczta.fm>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20180802013830.10600-1-jacekt@dugeo.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-09-10 10:03:01 +02:00
..
Makefile License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
bts.c x86,perf: Disable intel_bts when PTI 2018-01-14 11:42:10 +01:00
core.c perf/x86/intel: Support Extended PEBS for Goldmont Plus 2018-07-25 11:50:50 +02:00
cstate.c perf/x86/cstate: Fix possible Spectre-v1 indexing for pkg_msr 2018-05-05 08:37:31 +02:00
ds.c perf/x86/intel: Support Extended PEBS for Goldmont Plus 2018-07-25 11:50:50 +02:00
knc.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
lbr.c perf/x86/intel: Add support/quirk for the MISPREDICT bit on Knights Landing CPUs 2018-09-10 10:03:01 +02:00
p4.c x86: Mark various structures and functions as 'static' 2017-08-11 14:49:43 +02:00
p6.c x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping 2018-02-15 01:15:52 +01:00
pt.c perf/core: Fix bad use of igrab() 2018-05-25 08:11:10 +02:00
pt.h perf/x86/intel/pt: Allow the disabling of branch tracing 2017-03-30 09:53:49 +02:00
rapl.c perf/x86/intel: Add Cannon Lake support for RAPL profiling 2018-03-31 11:28:36 +02:00
uncore.c treewide: kzalloc() -> kcalloc() 2018-06-12 16:19:22 -07:00
uncore.h perf/x86/intel/uncore: Fix hardcoded index of Broadwell extra PCI devices 2018-07-31 07:43:37 +02:00
uncore_nhmex.c perf/x86/intel/uncore: Correct fixed counter index check for NHM 2018-05-31 12:36:28 +02:00
uncore_snb.c perf/x86/intel/uncore: Clean up client IMC uncore 2018-05-31 12:36:29 +02:00
uncore_snbep.c perf/x86/intel/uncore: Fix hardcoded index of Broadwell extra PCI devices 2018-07-31 07:43:37 +02:00