mirror of https://gitee.com/openkylin/linux.git
274 lines
8.5 KiB
C
274 lines
8.5 KiB
C
/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <drm/drmP.h>
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#include "meson_drv.h"
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#include "meson_venc.h"
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#include "meson_vpp.h"
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#include "meson_vclk.h"
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#include "meson_registers.h"
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/*
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* VENC Handle the pixels encoding to the output formats.
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* We handle the following encodings :
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* - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
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*
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* What is missing :
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* - TMDS/HDMI Encoding via ENCI_DIV and ENCP
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* - Setup of more clock rates for HDMI modes
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* - LCD Panel encoding via ENCL
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* - TV Panel encoding via ENCT
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*/
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/* HHI Registers */
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#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
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#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
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#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
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struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
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.mode_tag = MESON_VENC_MODE_CVBS_PAL,
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.hso_begin = 3,
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.hso_end = 129,
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.vso_even = 3,
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.vso_odd = 260,
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.macv_max_amp = 7,
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.video_prog_mode = 0xff,
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.video_mode = 0x13,
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.sch_adjust = 0x28,
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.yc_delay = 0x343,
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.pixel_start = 251,
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.pixel_end = 1691,
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.top_field_line_start = 22,
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.top_field_line_end = 310,
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.bottom_field_line_start = 23,
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.bottom_field_line_end = 311,
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.video_saturation = 9,
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.video_contrast = 0,
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.video_brightness = 0,
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.video_hue = 0,
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.analog_sync_adj = 0x8080,
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};
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struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = {
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.mode_tag = MESON_VENC_MODE_CVBS_NTSC,
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.hso_begin = 5,
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.hso_end = 129,
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.vso_even = 3,
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.vso_odd = 260,
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.macv_max_amp = 0xb,
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.video_prog_mode = 0xf0,
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.video_mode = 0x8,
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.sch_adjust = 0x20,
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.yc_delay = 0x333,
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.pixel_start = 227,
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.pixel_end = 1667,
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.top_field_line_start = 18,
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.top_field_line_end = 258,
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.bottom_field_line_start = 19,
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.bottom_field_line_end = 259,
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.video_saturation = 18,
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.video_contrast = 3,
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.video_brightness = 0,
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.video_hue = 0,
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.analog_sync_adj = 0x9c00,
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};
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void meson_venci_cvbs_mode_set(struct meson_drm *priv,
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struct meson_cvbs_enci_mode *mode)
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{
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if (mode->mode_tag == priv->venc.current_mode)
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return;
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/* CVBS Filter settings */
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writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
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writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
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/* Digital Video Select : Interlace, clk27 clk, external */
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writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
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/* Reset Video Mode */
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writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
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writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
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/* Horizontal sync signal output */
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writel_relaxed(mode->hso_begin,
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priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
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writel_relaxed(mode->hso_end,
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priv->io_base + _REG(ENCI_SYNC_HSO_END));
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/* Vertical Sync lines */
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writel_relaxed(mode->vso_even,
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priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
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writel_relaxed(mode->vso_odd,
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priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
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/* Macrovision max amplitude change */
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writel_relaxed(0x8100 + mode->macv_max_amp,
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priv->io_base + _REG(ENCI_MACV_MAX_AMP));
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/* Video mode */
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writel_relaxed(mode->video_prog_mode,
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priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
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writel_relaxed(mode->video_mode,
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priv->io_base + _REG(ENCI_VIDEO_MODE));
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/* Advanced Video Mode :
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* Demux shifting 0x2
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* Blank line end at line17/22
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* High bandwidth Luma Filter
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* Low bandwidth Chroma Filter
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* Bypass luma low pass filter
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* No macrovision on CSYNC
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*/
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writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
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writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
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/* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
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writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
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/* 0x3 Y, C, and Component Y delay */
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writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
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/* Timings */
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writel_relaxed(mode->pixel_start,
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priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
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writel_relaxed(mode->pixel_end,
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priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
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writel_relaxed(mode->top_field_line_start,
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priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
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writel_relaxed(mode->top_field_line_end,
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priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
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writel_relaxed(mode->bottom_field_line_start,
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priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
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writel_relaxed(mode->bottom_field_line_end,
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priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
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/* Internal Venc, Internal VIU Sync, Internal Vencoder */
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writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
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/* UNreset Interlaced TV Encoder */
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writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
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/* Enable Vfifo2vd, Y_Cb_Y_Cr select */
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writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
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/* Power UP Dacs */
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writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));
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/* Video Upsampling */
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writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
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writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
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writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
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/* Select Interlace Y DACs */
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writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
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writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
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writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
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writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
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writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
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writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
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/* Select ENCI for VIU */
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meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
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/* Enable ENCI FIFO */
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writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
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/* Select ENCI DACs 0, 1, 4, and 5 */
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writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
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writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
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/* Interlace video enable */
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writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
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/* Configure Video Saturation / Contrast / Brightness / Hue */
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writel_relaxed(mode->video_saturation,
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priv->io_base + _REG(ENCI_VIDEO_SAT));
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writel_relaxed(mode->video_contrast,
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priv->io_base + _REG(ENCI_VIDEO_CONT));
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writel_relaxed(mode->video_brightness,
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priv->io_base + _REG(ENCI_VIDEO_BRIGHT));
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writel_relaxed(mode->video_hue,
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priv->io_base + _REG(ENCI_VIDEO_HUE));
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/* Enable DAC0 Filter */
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writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
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writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
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/* 0 in Macrovision register 0 */
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writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0));
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/* Analog Synchronization and color burst value adjust */
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writel_relaxed(mode->analog_sync_adj,
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priv->io_base + _REG(ENCI_SYNC_ADJ));
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/* Setup 27MHz vclk2 for ENCI and VDAC */
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meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS, MESON_VCLK_CVBS);
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priv->venc.current_mode = mode->mode_tag;
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}
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/* Returns the current ENCI field polarity */
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unsigned int meson_venci_get_field(struct meson_drm *priv)
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{
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return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29);
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}
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void meson_venc_enable_vsync(struct meson_drm *priv)
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{
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writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL));
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}
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void meson_venc_disable_vsync(struct meson_drm *priv)
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{
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writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
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}
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void meson_venc_init(struct meson_drm *priv)
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{
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/* Disable CVBS VDAC */
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regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
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/* Power Down Dacs */
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writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
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/* Disable HDMI PHY */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
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/* Disable HDMI */
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writel_bits_relaxed(0x3, 0,
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priv->io_base + _REG(VPU_HDMI_SETTING));
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/* Disable all encoders */
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writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
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writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
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writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
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/* Disable VSync IRQ */
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meson_venc_disable_vsync(priv);
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priv->venc.current_mode = MESON_VENC_MODE_NONE;
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}
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