mirror of https://gitee.com/openkylin/linux.git
296 lines
5.7 KiB
C
296 lines
5.7 KiB
C
/* Applied Micro X-Gene SoC Ethernet Classifier structures
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*
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* Copyright (c) 2016, Applied Micro Circuits Corporation
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* Authors: Khuong Dinh <kdinh@apm.com>
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* Tanmay Inamdar <tinamdar@apm.com>
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* Iyappan Subramanian <isubramanian@apm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __XGENE_ENET_CLE_H__
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#define __XGENE_ENET_CLE_H__
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#include <linux/io.h>
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#include <linux/random.h>
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/* Register offsets */
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#define INDADDR 0x04
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#define INDCMD 0x08
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#define INDCMD_STATUS 0x0c
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#define DATA_RAM0 0x10
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#define SNPTR0 0x0100
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#define SPPTR0 0x0104
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#define DFCLSRESDBPTR0 0x0108
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#define DFCLSRESDB00 0x010c
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#define RSS_CTRL0 0x0000013c
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#define CLE_CMD_TO 10 /* ms */
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#define CLE_PKTRAM_SIZE 256 /* bytes */
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#define CLE_PORT_OFFSET 0x200
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#define CLE_DRAM_REGS 17
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#define CLE_DN_TYPE_LEN 2
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#define CLE_DN_TYPE_POS 0
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#define CLE_DN_LASTN_LEN 1
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#define CLE_DN_LASTN_POS 2
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#define CLE_DN_HLS_LEN 1
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#define CLE_DN_HLS_POS 3
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#define CLE_DN_EXT_LEN 2
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#define CLE_DN_EXT_POS 4
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#define CLE_DN_BSTOR_LEN 2
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#define CLE_DN_BSTOR_POS 6
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#define CLE_DN_SBSTOR_LEN 2
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#define CLE_DN_SBSTOR_POS 8
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#define CLE_DN_RPTR_LEN 12
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#define CLE_DN_RPTR_POS 12
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#define CLE_BR_VALID_LEN 1
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#define CLE_BR_VALID_POS 0
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#define CLE_BR_NPPTR_LEN 9
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#define CLE_BR_NPPTR_POS 1
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#define CLE_BR_JB_LEN 1
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#define CLE_BR_JB_POS 10
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#define CLE_BR_JR_LEN 1
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#define CLE_BR_JR_POS 11
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#define CLE_BR_OP_LEN 3
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#define CLE_BR_OP_POS 12
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#define CLE_BR_NNODE_LEN 9
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#define CLE_BR_NNODE_POS 15
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#define CLE_BR_NBR_LEN 5
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#define CLE_BR_NBR_POS 24
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#define CLE_BR_DATA_LEN 16
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#define CLE_BR_DATA_POS 0
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#define CLE_BR_MASK_LEN 16
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#define CLE_BR_MASK_POS 16
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#define CLE_KN_PRIO_POS 0
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#define CLE_KN_PRIO_LEN 3
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#define CLE_KN_RPTR_POS 3
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#define CLE_KN_RPTR_LEN 10
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#define CLE_TYPE_POS 0
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#define CLE_TYPE_LEN 2
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#define CLE_DSTQIDL_POS 25
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#define CLE_DSTQIDL_LEN 7
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#define CLE_DSTQIDH_POS 0
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#define CLE_DSTQIDH_LEN 5
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#define CLE_FPSEL_POS 21
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#define CLE_FPSEL_LEN 4
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#define CLE_PRIORITY_POS 5
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#define CLE_PRIORITY_LEN 3
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#define JMP_ABS 0
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#define JMP_REL 1
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#define JMP_FW 0
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#define JMP_BW 1
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enum xgene_cle_ptree_nodes {
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PKT_TYPE_NODE,
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PKT_PROT_NODE,
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RSS_IPV4_TCP_NODE,
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RSS_IPV4_UDP_NODE,
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LAST_NODE,
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MAX_NODES
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};
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enum xgene_cle_byte_store {
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NO_BYTE,
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FIRST_BYTE,
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SECOND_BYTE,
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BOTH_BYTES
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};
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/* Preclassification operation types */
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enum xgene_cle_node_type {
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INV,
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KN,
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EWDN,
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RES_NODE
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};
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/* Preclassification operation types */
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enum xgene_cle_op_type {
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EQT,
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NEQT,
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LTEQT,
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GTEQT,
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AND,
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NAND
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};
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enum xgene_cle_parser {
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PARSER0,
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PARSER1,
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PARSER2,
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PARSER_ALL
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};
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#define XGENE_CLE_DRAM(type) (((type) & 0xf) << 28)
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enum xgene_cle_dram_type {
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PKT_RAM,
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RSS_IDT,
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RSS_IPV4_HASH_SKEY,
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PTREE_RAM = 0xc,
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AVL_RAM,
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DB_RAM
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};
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enum xgene_cle_cmd_type {
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CLE_CMD_WR = 1,
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CLE_CMD_RD = 2,
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CLE_CMD_AVL_ADD = 8,
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CLE_CMD_AVL_DEL = 16,
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CLE_CMD_AVL_SRCH = 32
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};
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enum xgene_cle_ipv4_rss_hashtype {
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RSS_IPV4_8B,
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RSS_IPV4_12B,
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};
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enum xgene_cle_prot_type {
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XGENE_CLE_TCP,
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XGENE_CLE_UDP,
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XGENE_CLE_ESP,
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XGENE_CLE_OTHER
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};
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enum xgene_cle_prot_version {
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XGENE_CLE_IPV4,
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};
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enum xgene_cle_ptree_dbptrs {
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DB_RES_DROP,
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DB_RES_DEF,
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DB_RES_ACCEPT,
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DB_MAX_PTRS
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};
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/* RSS sideband signal info */
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#define SB_IPFRAG_POS 0
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#define SB_IPFRAG_LEN 1
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#define SB_IPPROT_POS 1
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#define SB_IPPROT_LEN 2
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#define SB_IPVER_POS 3
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#define SB_IPVER_LEN 1
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#define SB_HDRLEN_POS 4
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#define SB_HDRLEN_LEN 12
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/* RSS indirection table */
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#define XGENE_CLE_IDT_ENTRIES 128
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#define IDT_DSTQID_POS 0
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#define IDT_DSTQID_LEN 12
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#define IDT_FPSEL_POS 12
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#define IDT_FPSEL_LEN 4
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#define IDT_NFPSEL_POS 16
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#define IDT_NFPSEL_LEN 4
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struct xgene_cle_ptree_branch {
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bool valid;
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u16 next_packet_pointer;
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bool jump_bw;
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bool jump_rel;
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u8 operation;
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u16 next_node;
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u8 next_branch;
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u16 data;
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u16 mask;
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};
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struct xgene_cle_ptree_ewdn {
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u8 node_type;
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bool last_node;
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bool hdr_len_store;
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u8 hdr_extn;
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u8 byte_store;
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u8 search_byte_store;
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u16 result_pointer;
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u8 num_branches;
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struct xgene_cle_ptree_branch branch[6];
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};
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struct xgene_cle_ptree_key {
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u8 priority;
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u16 result_pointer;
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};
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struct xgene_cle_ptree_kn {
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u8 node_type;
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u8 num_keys;
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struct xgene_cle_ptree_key key[32];
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};
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struct xgene_cle_dbptr {
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u8 split_boundary;
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u8 mirror_nxtfpsel;
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u8 mirror_fpsel;
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u16 mirror_dstqid;
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u8 drop;
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u8 mirror;
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u8 hdr_data_split;
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u64 hopinfomsbs;
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u8 DR;
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u8 HR;
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u64 hopinfomlsbs;
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u16 h0enq_num;
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u8 h0fpsel;
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u8 nxtfpsel;
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u8 fpsel;
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u16 dstqid;
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u8 cle_priority;
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u8 cle_flowgroup;
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u8 cle_perflow;
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u8 cle_insert_timestamp;
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u8 stash;
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u8 in;
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u8 perprioen;
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u8 perflowgroupen;
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u8 perflowen;
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u8 selhash;
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u8 selhdrext;
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u8 mirror_nxtfpsel_msb;
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u8 mirror_fpsel_msb;
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u8 hfpsel_msb;
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u8 nxtfpsel_msb;
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u8 fpsel_msb;
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};
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struct xgene_cle_ptree {
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struct xgene_cle_ptree_ewdn *dn;
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struct xgene_cle_ptree_kn *kn;
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struct xgene_cle_dbptr *dbptr;
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u32 num_dn;
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u32 num_kn;
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u32 num_dbptr;
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u32 start_node;
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u32 start_pkt;
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u32 start_dbptr;
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};
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struct xgene_enet_cle {
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void __iomem *base;
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struct xgene_cle_ptree ptree;
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enum xgene_cle_parser active_parser;
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u32 parsers;
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u32 max_nodes;
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u32 max_dbptrs;
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u32 jump_bytes;
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};
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extern struct xgene_cle_ops xgene_cle3in_ops;
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#endif /* __XGENE_ENET_CLE_H__ */
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