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225 lines
6.8 KiB
Plaintext
225 lines
6.8 KiB
Plaintext
ARM Versatile Express boards family
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-----------------------------------
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ARM's Versatile Express platform consists of a motherboard and one
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or more daughterboards (tiles). The motherboard provides a set of
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peripherals. Processor and RAM "live" on the tiles.
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The motherboard and each core tile should be described by a separate
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Device Tree source file, with the tile's description including
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the motherboard file using a /include/ directive. As the motherboard
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can be initialized in one of two different configurations ("memory
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maps"), care must be taken to include the correct one.
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Root node
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---------
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Required properties in the root node:
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- compatible value:
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compatible = "arm,vexpress,<model>", "arm,vexpress";
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where <model> is the full tile model name (as used in the tile's
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Technical Reference Manual), eg.:
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- for Coretile Express A5x2 (V2P-CA5s):
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compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
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- for Coretile Express A9x4 (V2P-CA9):
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compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
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If a tile comes in several variants or can be used in more then one
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configuration, the compatible value should be:
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compatible = "arm,vexpress,<model>,<variant>", \
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"arm,vexpress,<model>", "arm,vexpress";
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eg:
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- Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
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compatible = "arm,vexpress,v2p-ca15,tc1", \
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"arm,vexpress,v2p-ca15", "arm,vexpress";
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- LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
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compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
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"arm,vexpress,v2f-2xv6", "arm,vexpress";
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Optional properties in the root node:
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- tile model name (use name from the tile's Technical Reference
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Manual, eg. "V2P-CA5s")
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model = "<model>";
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- tile's HBI number (unique ARM's board model ID, visible on the
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PCB's silkscreen) in hexadecimal transcription:
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arm,hbi = <0xhbi>
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eg:
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- for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
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arm,hbi = <0x191>;
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- Coretile Express A9x4 (V2P-CA9) HBI-0225:
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arm,hbi = <0x225>;
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CPU nodes
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---------
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Top-level standard "cpus" node is required. It must contain a node
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with device_type = "cpu" property for every available core, eg.:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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};
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};
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Configuration infrastructure
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----------------------------
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The platform has an elaborated configuration system, consisting of
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microcontrollers residing on the mother- and daughterboards known
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as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
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The controllers are responsible for the platform initialization
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(reset generation, flash programming, FPGA bitfiles loading etc.)
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but also control clock generators, voltage regulators, gather
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environmental data like temperature, power consumption etc. Even
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the video output switch (FPGA) is controlled that way.
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Nodes describing devices controlled by this infrastructure should
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point at the bridge device node:
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- bridge phandle:
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arm,vexpress,config-bridge = <phandle>;
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This property can be also defined in a parent node (eg. for a DCC)
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and is effective for all children.
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Platform topology
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-----------------
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As Versatile Express can be configured in number of physically
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different setups, the device tree should describe platform topology.
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Root node and main motherboard node must define the following
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property, describing physical location of the children nodes:
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- site number:
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arm,vexpress,site = <number>;
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where 0 means motherboard, 1 or 2 are daugtherboard sites,
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0xf means "master" site (site containing main CPU tile)
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- when daughterboards are stacked on one site, their position
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in the stack be be described with:
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arm,vexpress,position = <number>;
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- when describing tiles consisting more than one DCC, its number
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can be described with:
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arm,vexpress,dcc = <number>;
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Any of the numbers above defaults to zero if not defined in
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the node or any of its parent.
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Motherboard
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-----------
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The motherboard description file provides a single "motherboard" node
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using 2 address cells corresponding to the Static Memory Bus used
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between the motherboard and the tile. The first cell defines the Chip
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Select (CS) line number, the second cell address offset within the CS.
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All interrupt lines between the motherboard and the tile are active
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high and are described using single cell.
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Optional properties of the "motherboard" node:
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- motherboard's memory map variant:
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arm,v2m-memory-map = "<name>";
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where name is one of:
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- "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
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referred to as "ARM Cortex-A Series memory map":
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arm,v2m-memory-map = "rs1";
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When this property is missing, the motherboard is using the original
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memory map (also known as the "Legacy memory map", primarily used
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with the original CoreTile Express A9x4) with peripherals on CS7.
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Motherboard .dtsi files provide a set of labelled peripherals that
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can be used to obtain required phandle in the tile's "aliases" node:
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- UARTs, note that the numbers correspond to the physical connectors
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on the motherboard's back panel:
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v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
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- I2C controllers:
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v2m_i2c_dvi and v2m_i2c_pcie
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- SP804 timers:
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v2m_timer01 and v2m_timer23
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The tile description should define a "smb" node, describing the
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Static Memory Bus between the tile and motherboard. It must define
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the following properties:
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- "simple-bus" compatible value (to ensure creation of the children)
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compatible = "simple-bus";
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- mapping of the SMB CS/offset addresses into main address space:
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <...>;
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- interrupts mapping:
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <...>;
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Example of a VE tile description (simplified)
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---------------------------------------------
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/dts-v1/;
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/ {
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model = "V2P-CA5s";
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arm,hbi = <0x225>;
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arm,vexpress,site = <0xf>;
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compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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};
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x2c001000 0x1000>,
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<0x2c000100 0x100>;
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};
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dcc {
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compatible = "simple-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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osc@0 {
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compatible = "arm,vexpress-osc";
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};
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};
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smb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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/* CS0 is visible at 0x08000000 */
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ranges = <0 0 0x08000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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/* Active high IRQ 0 is connected to GIC's SPI0 */
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interrupt-map = <0 0 0 &gic 0 0 4>;
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/include/ "vexpress-v2m-rs1.dtsi"
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};
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};
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