mirror of https://gitee.com/openkylin/linux.git
782 lines
18 KiB
Plaintext
782 lines
18 KiB
Plaintext
/include/ "skeleton.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
|
|
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
|
|
|
/ {
|
|
compatible = "marvell,dove";
|
|
model = "Marvell Armada 88AP510 SoC";
|
|
interrupt-parent = <&intc>;
|
|
|
|
aliases {
|
|
gpio0 = &gpio0;
|
|
gpio1 = &gpio1;
|
|
gpio2 = &gpio2;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
compatible = "marvell,pj4a", "marvell,sheeva-v7";
|
|
device_type = "cpu";
|
|
next-level-cache = <&l2>;
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
l2: l2-cache {
|
|
compatible = "marvell,tauros2-cache";
|
|
marvell,tauros2-cache-features = <0>;
|
|
};
|
|
|
|
i2c-mux {
|
|
compatible = "i2c-mux-pinctrl";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
i2c-parent = <&i2c>;
|
|
|
|
pinctrl-names = "i2c0", "i2c1", "i2c2";
|
|
pinctrl-0 = <&pmx_i2cmux_0>;
|
|
pinctrl-1 = <&pmx_i2cmux_1>;
|
|
pinctrl-2 = <&pmx_i2cmux_2>;
|
|
|
|
i2c0: i2c@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "okay";
|
|
};
|
|
|
|
i2c1: i2c@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
/* Requires pmx_i2c1 on i2c controller node */
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@2 {
|
|
reg = <2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
/* Requires pmx_i2c2 on i2c controller node */
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
mbus {
|
|
compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
controller = <&mbusc>;
|
|
pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
|
|
pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
|
|
|
|
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
|
|
MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
|
|
MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
|
|
MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
|
|
MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
|
|
|
|
pcie: pcie-controller {
|
|
compatible = "marvell,dove-pcie";
|
|
status = "disabled";
|
|
device_type = "pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
msi-parent = <&intc>;
|
|
bus-range = <0x00 0xff>;
|
|
|
|
ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
|
|
0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
|
|
0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
|
|
0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
|
|
0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
|
|
0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
|
|
|
|
pcie0: pcie-port@0 {
|
|
device_type = "pci";
|
|
status = "disabled";
|
|
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
|
reg = <0x0800 0 0 0 0>;
|
|
clocks = <&gate_clk 4>;
|
|
marvell,pcie-port = <0>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
|
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &intc 16>;
|
|
};
|
|
|
|
pcie1: pcie-port@1 {
|
|
device_type = "pci";
|
|
status = "disabled";
|
|
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
|
reg = <0x1000 0 0 0 0>;
|
|
clocks = <&gate_clk 5>;
|
|
marvell,pcie-port = <1>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
|
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &intc 18>;
|
|
};
|
|
};
|
|
|
|
internal-regs {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
|
|
0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
|
|
0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
|
|
0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
|
|
|
|
spi0: spi-ctrl@10600 {
|
|
compatible = "marvell,orion-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
interrupts = <6>;
|
|
reg = <0x10600 0x28>;
|
|
clocks = <&core_clk 0>;
|
|
pinctrl-0 = <&pmx_spi0>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c: i2c-ctrl@11000 {
|
|
compatible = "marvell,mv64xxx-i2c";
|
|
reg = <0x11000 0x20>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <11>;
|
|
clock-frequency = <400000>;
|
|
timeout-ms = <1000>;
|
|
clocks = <&core_clk 0>;
|
|
status = "okay";
|
|
};
|
|
|
|
uart0: serial@12000 {
|
|
compatible = "ns16550a";
|
|
reg = <0x12000 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <7>;
|
|
clocks = <&core_clk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@12100 {
|
|
compatible = "ns16550a";
|
|
reg = <0x12100 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <8>;
|
|
clocks = <&core_clk 0>;
|
|
pinctrl-0 = <&pmx_uart1>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@12200 {
|
|
compatible = "ns16550a";
|
|
reg = <0x12200 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <9>;
|
|
clocks = <&core_clk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@12300 {
|
|
compatible = "ns16550a";
|
|
reg = <0x12300 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <10>;
|
|
clocks = <&core_clk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi-ctrl@14600 {
|
|
compatible = "marvell,orion-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <1>;
|
|
interrupts = <5>;
|
|
reg = <0x14600 0x28>;
|
|
clocks = <&core_clk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mbusc: mbus-ctrl@20000 {
|
|
compatible = "marvell,mbus-controller";
|
|
reg = <0x20000 0x80>, <0x800100 0x8>;
|
|
};
|
|
|
|
sysc: system-ctrl@20000 {
|
|
compatible = "marvell,orion-system-controller";
|
|
reg = <0x20000 0x110>;
|
|
};
|
|
|
|
bridge_intc: bridge-interrupt-ctrl@20110 {
|
|
compatible = "marvell,orion-bridge-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x20110 0x8>;
|
|
interrupts = <0>;
|
|
marvell,#interrupts = <5>;
|
|
};
|
|
|
|
intc: main-interrupt-ctrl@20200 {
|
|
compatible = "marvell,orion-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x20200 0x10>, <0x20210 0x10>;
|
|
};
|
|
|
|
timer: timer@20300 {
|
|
compatible = "marvell,orion-timer";
|
|
reg = <0x20300 0x20>;
|
|
interrupt-parent = <&bridge_intc>;
|
|
interrupts = <1>, <2>;
|
|
clocks = <&core_clk 0>;
|
|
};
|
|
|
|
watchdog@20300 {
|
|
compatible = "marvell,orion-wdt";
|
|
reg = <0x20300 0x28>, <0x20108 0x4>;
|
|
interrupt-parent = <&bridge_intc>;
|
|
interrupts = <3>;
|
|
clocks = <&core_clk 0>;
|
|
};
|
|
|
|
crypto: crypto-engine@30000 {
|
|
compatible = "marvell,orion-crypto";
|
|
reg = <0x30000 0x10000>;
|
|
reg-names = "regs";
|
|
interrupts = <31>;
|
|
clocks = <&gate_clk 15>;
|
|
marvell,crypto-srams = <&crypto_sram>;
|
|
marvell,crypto-sram-size = <0x800>;
|
|
status = "okay";
|
|
};
|
|
|
|
ehci0: usb-host@50000 {
|
|
compatible = "marvell,orion-ehci";
|
|
reg = <0x50000 0x1000>;
|
|
interrupts = <24>;
|
|
clocks = <&gate_clk 0>;
|
|
status = "okay";
|
|
};
|
|
|
|
ehci1: usb-host@51000 {
|
|
compatible = "marvell,orion-ehci";
|
|
reg = <0x51000 0x1000>;
|
|
interrupts = <25>;
|
|
clocks = <&gate_clk 1>;
|
|
status = "okay";
|
|
};
|
|
|
|
xor0: dma-engine@60800 {
|
|
compatible = "marvell,orion-xor";
|
|
reg = <0x60800 0x100
|
|
0x60a00 0x100>;
|
|
clocks = <&gate_clk 23>;
|
|
status = "okay";
|
|
|
|
channel0 {
|
|
interrupts = <39>;
|
|
dmacap,memcpy;
|
|
dmacap,xor;
|
|
};
|
|
|
|
channel1 {
|
|
interrupts = <40>;
|
|
dmacap,memcpy;
|
|
dmacap,xor;
|
|
};
|
|
};
|
|
|
|
xor1: dma-engine@60900 {
|
|
compatible = "marvell,orion-xor";
|
|
reg = <0x60900 0x100
|
|
0x60b00 0x100>;
|
|
clocks = <&gate_clk 24>;
|
|
status = "okay";
|
|
|
|
channel0 {
|
|
interrupts = <42>;
|
|
dmacap,memcpy;
|
|
dmacap,xor;
|
|
};
|
|
|
|
channel1 {
|
|
interrupts = <43>;
|
|
dmacap,memcpy;
|
|
dmacap,xor;
|
|
};
|
|
};
|
|
|
|
sdio1: sdio-host@90000 {
|
|
compatible = "marvell,dove-sdhci";
|
|
reg = <0x90000 0x100>;
|
|
interrupts = <36>, <38>;
|
|
clocks = <&gate_clk 9>;
|
|
pinctrl-0 = <&pmx_sdio1>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
eth: ethernet-ctrl@72000 {
|
|
compatible = "marvell,orion-eth";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x72000 0x4000>;
|
|
clocks = <&gate_clk 2>;
|
|
marvell,tx-checksum-limit = <1600>;
|
|
status = "disabled";
|
|
|
|
ethernet-port@0 {
|
|
compatible = "marvell,orion-eth-port";
|
|
reg = <0>;
|
|
interrupts = <29>;
|
|
/* overwrite MAC address in bootloader */
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
phy-handle = <ðphy>;
|
|
};
|
|
};
|
|
|
|
mdio: mdio-bus@72004 {
|
|
compatible = "marvell,orion-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x72004 0x84>;
|
|
interrupts = <30>;
|
|
clocks = <&gate_clk 2>;
|
|
status = "disabled";
|
|
|
|
ethphy: ethernet-phy {
|
|
/* set phy address in board file */
|
|
};
|
|
};
|
|
|
|
sdio0: sdio-host@92000 {
|
|
compatible = "marvell,dove-sdhci";
|
|
reg = <0x92000 0x100>;
|
|
interrupts = <35>, <37>;
|
|
clocks = <&gate_clk 8>;
|
|
pinctrl-0 = <&pmx_sdio0>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
sata0: sata-host@a0000 {
|
|
compatible = "marvell,orion-sata";
|
|
reg = <0xa0000 0x2400>;
|
|
interrupts = <62>;
|
|
clocks = <&gate_clk 3>;
|
|
phys = <&sata_phy0>;
|
|
phy-names = "port0";
|
|
nr-ports = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata_phy0: sata-phy@a2000 {
|
|
compatible = "marvell,mvebu-sata-phy";
|
|
reg = <0xa2000 0x0334>;
|
|
clocks = <&gate_clk 3>;
|
|
clock-names = "sata";
|
|
#phy-cells = <0>;
|
|
status = "ok";
|
|
};
|
|
|
|
audio0: audio-controller@b0000 {
|
|
compatible = "marvell,dove-audio";
|
|
reg = <0xb0000 0x2210>;
|
|
interrupts = <19>, <20>;
|
|
clocks = <&gate_clk 12>;
|
|
clock-names = "internal";
|
|
status = "disabled";
|
|
};
|
|
|
|
audio1: audio-controller@b4000 {
|
|
compatible = "marvell,dove-audio";
|
|
reg = <0xb4000 0x2210>;
|
|
interrupts = <21>, <22>;
|
|
clocks = <&gate_clk 13>;
|
|
clock-names = "internal";
|
|
status = "disabled";
|
|
};
|
|
|
|
pmu: power-management@d0000 {
|
|
compatible = "marvell,dove-pmu", "simple-bus";
|
|
reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
|
|
ranges = <0x00000000 0x000d0000 0x8000
|
|
0x00008000 0x000d8000 0x8000>;
|
|
interrupts = <33>;
|
|
interrupt-controller;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
#interrupt-cells = <1>;
|
|
#reset-cells = <1>;
|
|
|
|
domains {
|
|
vpu_domain: vpu-domain {
|
|
#power-domain-cells = <0>;
|
|
marvell,pmu_pwr_mask = <0x00000008>;
|
|
marvell,pmu_iso_mask = <0x00000001>;
|
|
resets = <&pmu 16>;
|
|
};
|
|
|
|
gpu_domain: gpu-domain {
|
|
#power-domain-cells = <0>;
|
|
marvell,pmu_pwr_mask = <0x00000004>;
|
|
marvell,pmu_iso_mask = <0x00000002>;
|
|
resets = <&pmu 18>;
|
|
};
|
|
};
|
|
|
|
thermal: thermal-diode@001c {
|
|
compatible = "marvell,dove-thermal";
|
|
reg = <0x001c 0x0c>, <0x005c 0x08>;
|
|
};
|
|
|
|
gate_clk: clock-gating-ctrl@0038 {
|
|
compatible = "marvell,dove-gating-clock";
|
|
reg = <0x0038 0x4>;
|
|
clocks = <&core_clk 0>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pinctrl: pin-ctrl@0200 {
|
|
compatible = "marvell,dove-pinctrl";
|
|
reg = <0x0200 0x14>,
|
|
<0x0440 0x04>;
|
|
clocks = <&gate_clk 22>;
|
|
|
|
pmx_gpio_0: pmx-gpio-0 {
|
|
marvell,pins = "mpp0";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_1: pmx-gpio-1 {
|
|
marvell,pins = "mpp1";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_2: pmx-gpio-2 {
|
|
marvell,pins = "mpp2";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_3: pmx-gpio-3 {
|
|
marvell,pins = "mpp3";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_4: pmx-gpio-4 {
|
|
marvell,pins = "mpp4";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_5: pmx-gpio-5 {
|
|
marvell,pins = "mpp5";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_6: pmx-gpio-6 {
|
|
marvell,pins = "mpp6";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_7: pmx-gpio-7 {
|
|
marvell,pins = "mpp7";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_8: pmx-gpio-8 {
|
|
marvell,pins = "mpp8";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_9: pmx-gpio-9 {
|
|
marvell,pins = "mpp9";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_pcie1_clkreq: pmx-pcie1-clkreq {
|
|
marvell,pins = "mpp9";
|
|
marvell,function = "pex1";
|
|
};
|
|
|
|
pmx_gpio_10: pmx-gpio-10 {
|
|
marvell,pins = "mpp10";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_11: pmx-gpio-11 {
|
|
marvell,pins = "mpp11";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_pcie0_clkreq: pmx-pcie0-clkreq {
|
|
marvell,pins = "mpp11";
|
|
marvell,function = "pex0";
|
|
};
|
|
|
|
pmx_gpio_12: pmx-gpio-12 {
|
|
marvell,pins = "mpp12";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_13: pmx-gpio-13 {
|
|
marvell,pins = "mpp13";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_audio1_extclk: pmx-audio1-extclk {
|
|
marvell,pins = "mpp13";
|
|
marvell,function = "audio1";
|
|
};
|
|
|
|
pmx_gpio_14: pmx-gpio-14 {
|
|
marvell,pins = "mpp14";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_15: pmx-gpio-15 {
|
|
marvell,pins = "mpp15";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_16: pmx-gpio-16 {
|
|
marvell,pins = "mpp16";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_17: pmx-gpio-17 {
|
|
marvell,pins = "mpp17";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_18: pmx-gpio-18 {
|
|
marvell,pins = "mpp18";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_19: pmx-gpio-19 {
|
|
marvell,pins = "mpp19";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_20: pmx-gpio-20 {
|
|
marvell,pins = "mpp20";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_21: pmx-gpio-21 {
|
|
marvell,pins = "mpp21";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_camera: pmx-camera {
|
|
marvell,pins = "mpp_camera";
|
|
marvell,function = "camera";
|
|
};
|
|
|
|
pmx_camera_gpio: pmx-camera-gpio {
|
|
marvell,pins = "mpp_camera";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_sdio0: pmx-sdio0 {
|
|
marvell,pins = "mpp_sdio0";
|
|
marvell,function = "sdio0";
|
|
};
|
|
|
|
pmx_sdio0_gpio: pmx-sdio0-gpio {
|
|
marvell,pins = "mpp_sdio0";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_sdio1: pmx-sdio1 {
|
|
marvell,pins = "mpp_sdio1";
|
|
marvell,function = "sdio1";
|
|
};
|
|
|
|
pmx_sdio1_gpio: pmx-sdio1-gpio {
|
|
marvell,pins = "mpp_sdio1";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_audio1_gpio: pmx-audio1-gpio {
|
|
marvell,pins = "mpp_audio1";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
|
|
marvell,pins = "mpp_audio1";
|
|
marvell,function = "i2s1/spdifo";
|
|
};
|
|
|
|
pmx_spi0: pmx-spi0 {
|
|
marvell,pins = "mpp_spi0";
|
|
marvell,function = "spi0";
|
|
};
|
|
|
|
pmx_spi0_gpio: pmx-spi0-gpio {
|
|
marvell,pins = "mpp_spi0";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_spi1_4_7: pmx-spi1-4-7 {
|
|
marvell,pins = "mpp4", "mpp5",
|
|
"mpp6", "mpp7";
|
|
marvell,function = "spi1";
|
|
};
|
|
|
|
pmx_spi1_20_23: pmx-spi1-20-23 {
|
|
marvell,pins = "mpp20", "mpp21",
|
|
"mpp22", "mpp23";
|
|
marvell,function = "spi1";
|
|
};
|
|
|
|
pmx_uart1: pmx-uart1 {
|
|
marvell,pins = "mpp_uart1";
|
|
marvell,function = "uart1";
|
|
};
|
|
|
|
pmx_uart1_gpio: pmx-uart1-gpio {
|
|
marvell,pins = "mpp_uart1";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_nand: pmx-nand {
|
|
marvell,pins = "mpp_nand";
|
|
marvell,function = "nand";
|
|
};
|
|
|
|
pmx_nand_gpo: pmx-nand-gpo {
|
|
marvell,pins = "mpp_nand";
|
|
marvell,function = "gpo";
|
|
};
|
|
|
|
pmx_i2c1: pmx-i2c1 {
|
|
marvell,pins = "mpp17", "mpp19";
|
|
marvell,function = "twsi";
|
|
};
|
|
|
|
pmx_i2c2: pmx-i2c2 {
|
|
marvell,pins = "mpp_audio1";
|
|
marvell,function = "twsi";
|
|
};
|
|
|
|
pmx_ssp_i2c2: pmx-ssp-i2c2 {
|
|
marvell,pins = "mpp_audio1";
|
|
marvell,function = "ssp/twsi";
|
|
};
|
|
|
|
pmx_i2cmux_0: pmx-i2cmux-0 {
|
|
marvell,pins = "twsi";
|
|
marvell,function = "twsi-opt1";
|
|
};
|
|
|
|
pmx_i2cmux_1: pmx-i2cmux-1 {
|
|
marvell,pins = "twsi";
|
|
marvell,function = "twsi-opt2";
|
|
};
|
|
|
|
pmx_i2cmux_2: pmx-i2cmux-2 {
|
|
marvell,pins = "twsi";
|
|
marvell,function = "twsi-opt3";
|
|
};
|
|
};
|
|
|
|
core_clk: core-clocks@0214 {
|
|
compatible = "marvell,dove-core-clock";
|
|
reg = <0x0214 0x4>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gpio0: gpio-ctrl@0400 {
|
|
compatible = "marvell,orion-gpio";
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
reg = <0x0400 0x20>;
|
|
ngpios = <32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <12>, <13>, <14>, <60>;
|
|
};
|
|
|
|
gpio1: gpio-ctrl@0420 {
|
|
compatible = "marvell,orion-gpio";
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
reg = <0x0420 0x20>;
|
|
ngpios = <32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <61>;
|
|
};
|
|
|
|
rtc: real-time-clock@8500 {
|
|
compatible = "marvell,orion-rtc";
|
|
reg = <0x8500 0x20>;
|
|
interrupts = <5>;
|
|
};
|
|
};
|
|
|
|
gconf: global-config@e802c {
|
|
compatible = "marvell,dove-global-config",
|
|
"syscon";
|
|
reg = <0xe802c 0x14>;
|
|
};
|
|
|
|
gpio2: gpio-ctrl@e8400 {
|
|
compatible = "marvell,orion-gpio";
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
reg = <0xe8400 0x0c>;
|
|
ngpios = <8>;
|
|
};
|
|
|
|
lcd1: lcd-controller@810000 {
|
|
compatible = "marvell,dove-lcd";
|
|
reg = <0x810000 0x1000>;
|
|
interrupts = <46>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lcd0: lcd-controller@820000 {
|
|
compatible = "marvell,dove-lcd";
|
|
reg = <0x820000 0x1000>;
|
|
interrupts = <47>;
|
|
status = "disabled";
|
|
};
|
|
|
|
crypto_sram: sa-sram@ffffe000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0xffffe000 0x800>;
|
|
clocks = <&gate_clk 15>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
};
|
|
};
|
|
};
|