mirror of https://gitee.com/openkylin/linux.git
134 lines
3.1 KiB
C
134 lines
3.1 KiB
C
/*
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* linux/arch/arm/mach-tegra/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* Copyright (C) 2009 Palm
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <asm/smp_scu.h>
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#include <mach/iomap.h>
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extern void tegra_secondary_startup(void);
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static DEFINE_SPINLOCK(boot_lock);
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static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
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#define EVP_CPU_RESET_VECTOR \
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(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
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#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
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(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
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#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
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(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long old_boot_vector;
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unsigned long boot_vector;
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unsigned long timeout;
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u32 reg;
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/* set the reset vector to point to the secondary_startup routine */
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boot_vector = virt_to_phys(tegra_secondary_startup);
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old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
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writel(boot_vector, EVP_CPU_RESET_VECTOR);
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/* enable cpu clock on cpu1 */
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reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
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writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
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reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
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writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
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smp_wmb();
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flush_cache_all();
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/* unhalt the cpu */
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writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
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break;
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udelay(10);
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}
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/* put the old boot vector back */
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writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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unsigned int i, ncores = scu_get_core_count(scu_base);
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if (ncores > NR_CPUS) {
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printk(KERN_ERR "Tegra: no. of cores (%u) greater than configured (%u), clipping\n",
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ncores, NR_CPUS);
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ncores = NR_CPUS;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(scu_base);
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}
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