mirror of https://gitee.com/openkylin/linux.git
318 lines
8.7 KiB
C
318 lines
8.7 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
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*
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* Portions of this file are derived from the ipw3945 project.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include "iwl-io.h"
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#include"iwl-csr.h"
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#include "iwl-debug.h"
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#define IWL_POLL_INTERVAL 10 /* microseconds */
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static inline void __iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
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{
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iwl_write32(trans, reg, iwl_read32(trans, reg) | mask);
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}
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static inline void __iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
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{
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iwl_write32(trans, reg, iwl_read32(trans, reg) & ~mask);
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}
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void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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__iwl_set_bit(trans, reg, mask);
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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__iwl_clear_bit(trans, reg, mask);
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout)
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{
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int t = 0;
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do {
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if ((iwl_read32(trans, addr) & mask) == (bits & mask))
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return t;
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udelay(IWL_POLL_INTERVAL);
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t += IWL_POLL_INTERVAL;
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} while (t < timeout);
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return -ETIMEDOUT;
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}
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int iwl_grab_nic_access_silent(struct iwl_trans *trans)
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{
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int ret;
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lockdep_assert_held(&trans->reg_lock);
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/* this bit wakes up the NIC */
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__iwl_set_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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/*
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* These bits say the device is running, and should keep running for
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* at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
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* but they do not indicate that embedded SRAM is restored yet;
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* 3945 and 4965 have volatile SRAM, and must save/restore contents
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* to/from host DRAM when sleeping/waking for power-saving.
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* Each direction takes approximately 1/4 millisecond; with this
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* overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
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* series of register accesses are expected (e.g. reading Event Log),
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* to keep device from sleeping.
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*
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* CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
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* SRAM is okay/restored. We don't check that here because this call
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* is just for hardware register access; but GP1 MAC_SLEEP check is a
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* good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
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*
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* 5000 series and later (including 1000 series) have non-volatile SRAM,
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* and do not save/restore SRAM when power cycling.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
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(CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
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CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
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if (ret < 0) {
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iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
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return -EIO;
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}
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return 0;
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}
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bool iwl_grab_nic_access(struct iwl_trans *trans)
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{
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int ret = iwl_grab_nic_access_silent(trans);
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if (unlikely(ret)) {
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u32 val = iwl_read32(trans, CSR_GP_CNTRL);
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WARN_ONCE(1, "Timeout waiting for hardware access "
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"(CSR_GP_CNTRL 0x%08x)\n", val);
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return false;
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}
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return true;
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}
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void iwl_release_nic_access(struct iwl_trans *trans)
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{
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lockdep_assert_held(&trans->reg_lock);
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__iwl_clear_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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/*
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* Above we read the CSR_GP_CNTRL register, which will flush
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* any previous writes, but we need the write that clears the
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* MAC_ACCESS_REQ bit to be performed before any other writes
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* scheduled on different CPUs (after we drop reg_lock).
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*/
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mmiowb();
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}
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u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
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{
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u32 value;
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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iwl_grab_nic_access(trans);
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value = iwl_read32(trans, reg);
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iwl_release_nic_access(trans);
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return value;
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}
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void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
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{
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_grab_nic_access(trans))) {
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iwl_write32(trans, reg, value);
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iwl_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
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int timeout)
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{
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int t = 0;
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do {
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if ((iwl_read_direct32(trans, addr) & mask) == mask)
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return t;
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udelay(IWL_POLL_INTERVAL);
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t += IWL_POLL_INTERVAL;
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} while (t < timeout);
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return -ETIMEDOUT;
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}
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static inline u32 __iwl_read_prph(struct iwl_trans *trans, u32 reg)
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{
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iwl_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
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return iwl_read32(trans, HBUS_TARG_PRPH_RDAT);
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}
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static inline void __iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
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{
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iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
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((addr & 0x0000FFFF) | (3 << 24)));
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iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
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}
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u32 iwl_read_prph(struct iwl_trans *trans, u32 reg)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&trans->reg_lock, flags);
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iwl_grab_nic_access(trans);
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val = __iwl_read_prph(trans, reg);
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iwl_release_nic_access(trans);
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return val;
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}
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void iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_grab_nic_access(trans))) {
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__iwl_write_prph(trans, addr, val);
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iwl_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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void iwl_set_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_grab_nic_access(trans))) {
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__iwl_write_prph(trans, reg,
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__iwl_read_prph(trans, reg) | mask);
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iwl_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 reg,
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u32 bits, u32 mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_grab_nic_access(trans))) {
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__iwl_write_prph(trans, reg,
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(__iwl_read_prph(trans, reg) & mask) | bits);
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iwl_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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void iwl_clear_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_grab_nic_access(trans))) {
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val = __iwl_read_prph(trans, reg);
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__iwl_write_prph(trans, reg, (val & ~mask));
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iwl_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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void _iwl_read_targ_mem_words(struct iwl_trans *trans, u32 addr,
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void *buf, int words)
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{
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unsigned long flags;
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int offs;
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u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_grab_nic_access(trans))) {
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iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
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for (offs = 0; offs < words; offs++)
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vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
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iwl_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr)
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{
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u32 value;
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_iwl_read_targ_mem_words(trans, addr, &value, 1);
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return value;
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}
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int _iwl_write_targ_mem_words(struct iwl_trans *trans, u32 addr,
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void *buf, int words)
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{
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unsigned long flags;
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int offs, result = 0;
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u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_grab_nic_access(trans))) {
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iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
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for (offs = 0; offs < words; offs++)
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iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
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iwl_release_nic_access(trans);
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} else
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result = -EBUSY;
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return result;
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}
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int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val)
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{
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return _iwl_write_targ_mem_words(trans, addr, &val, 1);
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}
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