mirror of https://gitee.com/openkylin/linux.git
294 lines
7.4 KiB
C
294 lines
7.4 KiB
C
/*
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* TLB flush routines for radix kernels.
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*
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* Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/mm.h>
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#include <linux/hugetlb.h>
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#include <linux/memblock.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
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#define RIC_FLUSH_TLB 0
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#define RIC_FLUSH_PWC 1
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#define RIC_FLUSH_ALL 2
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static inline void __tlbiel_pid(unsigned long pid, int set,
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unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = PPC_BIT(53); /* IS = 1 */
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rb |= set << PPC_BITLSHIFT(51);
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rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
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prs = 1; /* process scoped */
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r = 1; /* raidx format */
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asm volatile("ptesync": : :"memory");
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asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |"
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"(%2 << 17) | (%3 << 18) | (%4 << 21)"
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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asm volatile("ptesync": : :"memory");
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}
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/*
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* We use 128 set in radix mode and 256 set in hpt mode.
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*/
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static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
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{
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int set;
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for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
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__tlbiel_pid(pid, set, ric);
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}
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return;
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}
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static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = PPC_BIT(53); /* IS = 1 */
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rs = pid << PPC_BITLSHIFT(31);
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prs = 1; /* process scoped */
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r = 1; /* raidx format */
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asm volatile("ptesync": : :"memory");
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asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |"
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"(%2 << 17) | (%3 << 18) | (%4 << 21)"
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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static inline void _tlbiel_va(unsigned long va, unsigned long pid,
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unsigned long ap, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = va & ~(PPC_BITMASK(52, 63));
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rb |= ap << PPC_BITLSHIFT(58);
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rs = pid << PPC_BITLSHIFT(31);
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prs = 1; /* process scoped */
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r = 1; /* raidx format */
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asm volatile("ptesync": : :"memory");
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asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |"
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"(%2 << 17) | (%3 << 18) | (%4 << 21)"
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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asm volatile("ptesync": : :"memory");
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}
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static inline void _tlbie_va(unsigned long va, unsigned long pid,
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unsigned long ap, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = va & ~(PPC_BITMASK(52, 63));
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rb |= ap << PPC_BITLSHIFT(58);
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rs = pid << PPC_BITLSHIFT(31);
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prs = 1; /* process scoped */
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r = 1; /* raidx format */
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asm volatile("ptesync": : :"memory");
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asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |"
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"(%2 << 17) | (%3 << 18) | (%4 << 21)"
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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/*
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* Base TLB flushing operations:
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*
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes kernel pages
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*
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* - local_* variants of page and mm only apply to the current
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* processor
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*/
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void radix__local_flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned long pid;
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preempt_disable();
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pid = mm->context.id;
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if (pid != MMU_NO_CONTEXT)
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_tlbiel_pid(pid, RIC_FLUSH_ALL);
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preempt_enable();
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}
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EXPORT_SYMBOL(radix__local_flush_tlb_mm);
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void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
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{
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unsigned long pid;
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struct mm_struct *mm = tlb->mm;
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preempt_disable();
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pid = mm->context.id;
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if (pid != MMU_NO_CONTEXT)
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_tlbiel_pid(pid, RIC_FLUSH_PWC);
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preempt_enable();
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}
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EXPORT_SYMBOL(radix__local_flush_tlb_pwc);
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void radix___local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
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unsigned long ap, int nid)
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{
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unsigned long pid;
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preempt_disable();
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pid = mm ? mm->context.id : 0;
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if (pid != MMU_NO_CONTEXT)
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_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
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preempt_enable();
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}
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void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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#ifdef CONFIG_HUGETLB_PAGE
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/* need the return fix for nohash.c */
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if (vma && is_vm_hugetlb_page(vma))
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return __local_flush_hugetlb_page(vma, vmaddr);
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#endif
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radix___local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
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mmu_get_ap(mmu_virtual_psize), 0);
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}
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EXPORT_SYMBOL(radix__local_flush_tlb_page);
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#ifdef CONFIG_SMP
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static int mm_is_core_local(struct mm_struct *mm)
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{
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return cpumask_subset(mm_cpumask(mm),
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topology_sibling_cpumask(smp_processor_id()));
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}
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void radix__flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned long pid;
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preempt_disable();
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pid = mm->context.id;
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if (unlikely(pid == MMU_NO_CONTEXT))
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goto no_context;
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if (!mm_is_core_local(mm)) {
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int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
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if (lock_tlbie)
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raw_spin_lock(&native_tlbie_lock);
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_tlbie_pid(pid, RIC_FLUSH_ALL);
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if (lock_tlbie)
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raw_spin_unlock(&native_tlbie_lock);
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} else
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_tlbiel_pid(pid, RIC_FLUSH_ALL);
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no_context:
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preempt_enable();
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}
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EXPORT_SYMBOL(radix__flush_tlb_mm);
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void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
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{
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unsigned long pid;
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struct mm_struct *mm = tlb->mm;
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preempt_disable();
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pid = mm->context.id;
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if (unlikely(pid == MMU_NO_CONTEXT))
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goto no_context;
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if (!mm_is_core_local(mm)) {
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int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
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if (lock_tlbie)
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raw_spin_lock(&native_tlbie_lock);
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_tlbie_pid(pid, RIC_FLUSH_PWC);
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if (lock_tlbie)
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raw_spin_unlock(&native_tlbie_lock);
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} else
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_tlbiel_pid(pid, RIC_FLUSH_PWC);
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no_context:
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preempt_enable();
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}
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EXPORT_SYMBOL(radix__flush_tlb_pwc);
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void radix___flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
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unsigned long ap, int nid)
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{
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unsigned long pid;
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preempt_disable();
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pid = mm ? mm->context.id : 0;
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if (unlikely(pid == MMU_NO_CONTEXT))
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goto bail;
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if (!mm_is_core_local(mm)) {
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int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
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if (lock_tlbie)
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raw_spin_lock(&native_tlbie_lock);
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_tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
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if (lock_tlbie)
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raw_spin_unlock(&native_tlbie_lock);
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} else
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_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
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bail:
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preempt_enable();
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}
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void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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#ifdef CONFIG_HUGETLB_PAGE
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if (vma && is_vm_hugetlb_page(vma))
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return flush_hugetlb_page(vma, vmaddr);
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#endif
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radix___flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
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mmu_get_ap(mmu_virtual_psize), 0);
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}
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EXPORT_SYMBOL(radix__flush_tlb_page);
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#endif /* CONFIG_SMP */
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void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
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if (lock_tlbie)
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raw_spin_lock(&native_tlbie_lock);
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_tlbie_pid(0, RIC_FLUSH_ALL);
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if (lock_tlbie)
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raw_spin_unlock(&native_tlbie_lock);
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}
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EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
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/*
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* Currently, for range flushing, we just do a full mm flush. Because
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* we use this in code path where we don' track the page size.
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*/
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void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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radix__flush_tlb_mm(mm);
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}
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EXPORT_SYMBOL(radix__flush_tlb_range);
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void radix__tlb_flush(struct mmu_gather *tlb)
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{
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struct mm_struct *mm = tlb->mm;
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radix__flush_tlb_mm(mm);
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}
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