mirror of https://gitee.com/openkylin/linux.git
776 lines
21 KiB
C
776 lines
21 KiB
C
/*
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* Intel MIC Platform Software Stack (MPSS)
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*
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* Copyright(c) 2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* Intel MIC X100 DMA Driver.
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*
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* Adapted from IOAT dma driver.
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/seq_file.h>
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#include <linux/vmalloc.h>
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#include "mic_x100_dma.h"
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#define MIC_DMA_MAX_XFER_SIZE_CARD (1 * 1024 * 1024 -\
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MIC_DMA_ALIGN_BYTES)
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#define MIC_DMA_MAX_XFER_SIZE_HOST (1 * 1024 * 1024 >> 1)
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#define MIC_DMA_DESC_TYPE_SHIFT 60
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#define MIC_DMA_MEMCPY_LEN_SHIFT 46
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#define MIC_DMA_STAT_INTR_SHIFT 59
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/* high-water mark for pushing dma descriptors */
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static int mic_dma_pending_level = 4;
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/* Status descriptor is used to write a 64 bit value to a memory location */
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enum mic_dma_desc_format_type {
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MIC_DMA_MEMCPY = 1,
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MIC_DMA_STATUS,
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};
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static inline u32 mic_dma_hw_ring_inc(u32 val)
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{
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return (val + 1) % MIC_DMA_DESC_RX_SIZE;
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}
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static inline u32 mic_dma_hw_ring_dec(u32 val)
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{
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return val ? val - 1 : MIC_DMA_DESC_RX_SIZE - 1;
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}
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static inline void mic_dma_hw_ring_inc_head(struct mic_dma_chan *ch)
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{
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ch->head = mic_dma_hw_ring_inc(ch->head);
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}
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/* Prepare a memcpy desc */
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static inline void mic_dma_memcpy_desc(struct mic_dma_desc *desc,
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dma_addr_t src_phys, dma_addr_t dst_phys, u64 size)
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{
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u64 qw0, qw1;
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qw0 = src_phys;
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qw0 |= (size >> MIC_DMA_ALIGN_SHIFT) << MIC_DMA_MEMCPY_LEN_SHIFT;
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qw1 = MIC_DMA_MEMCPY;
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qw1 <<= MIC_DMA_DESC_TYPE_SHIFT;
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qw1 |= dst_phys;
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desc->qw0 = qw0;
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desc->qw1 = qw1;
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}
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/* Prepare a status desc. with @data to be written at @dst_phys */
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static inline void mic_dma_prep_status_desc(struct mic_dma_desc *desc, u64 data,
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dma_addr_t dst_phys, bool generate_intr)
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{
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u64 qw0, qw1;
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qw0 = data;
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qw1 = (u64) MIC_DMA_STATUS << MIC_DMA_DESC_TYPE_SHIFT | dst_phys;
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if (generate_intr)
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qw1 |= (1ULL << MIC_DMA_STAT_INTR_SHIFT);
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desc->qw0 = qw0;
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desc->qw1 = qw1;
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}
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static void mic_dma_cleanup(struct mic_dma_chan *ch)
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{
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struct dma_async_tx_descriptor *tx;
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u32 tail;
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u32 last_tail;
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spin_lock(&ch->cleanup_lock);
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tail = mic_dma_read_cmp_cnt(ch);
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/*
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* This is the barrier pair for smp_wmb() in fn.
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* mic_dma_tx_submit_unlock. It's required so that we read the
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* updated cookie value from tx->cookie.
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*/
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smp_rmb();
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for (last_tail = ch->last_tail; tail != last_tail;) {
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tx = &ch->tx_array[last_tail];
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if (tx->cookie) {
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dma_cookie_complete(tx);
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if (tx->callback) {
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tx->callback(tx->callback_param);
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tx->callback = NULL;
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}
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}
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last_tail = mic_dma_hw_ring_inc(last_tail);
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}
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/* finish all completion callbacks before incrementing tail */
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smp_mb();
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ch->last_tail = last_tail;
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spin_unlock(&ch->cleanup_lock);
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}
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static u32 mic_dma_ring_count(u32 head, u32 tail)
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{
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u32 count;
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if (head >= tail)
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count = (tail - 0) + (MIC_DMA_DESC_RX_SIZE - head);
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else
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count = tail - head;
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return count - 1;
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}
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/* Returns the num. of free descriptors on success, -ENOMEM on failure */
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static int mic_dma_avail_desc_ring_space(struct mic_dma_chan *ch, int required)
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{
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struct device *dev = mic_dma_ch_to_device(ch);
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u32 count;
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count = mic_dma_ring_count(ch->head, ch->last_tail);
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if (count < required) {
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mic_dma_cleanup(ch);
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count = mic_dma_ring_count(ch->head, ch->last_tail);
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}
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if (count < required) {
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dev_dbg(dev, "Not enough desc space");
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dev_dbg(dev, "%s %d required=%u, avail=%u\n",
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__func__, __LINE__, required, count);
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return -ENOMEM;
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} else {
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return count;
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}
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}
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/* Program memcpy descriptors into the descriptor ring and update s/w head ptr*/
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static int mic_dma_prog_memcpy_desc(struct mic_dma_chan *ch, dma_addr_t src,
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dma_addr_t dst, size_t len)
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{
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size_t current_transfer_len;
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size_t max_xfer_size = to_mic_dma_dev(ch)->max_xfer_size;
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/* 3 is added to make sure we have enough space for status desc */
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int num_desc = len / max_xfer_size + 3;
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int ret;
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if (len % max_xfer_size)
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num_desc++;
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ret = mic_dma_avail_desc_ring_space(ch, num_desc);
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if (ret < 0)
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return ret;
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do {
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current_transfer_len = min(len, max_xfer_size);
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mic_dma_memcpy_desc(&ch->desc_ring[ch->head],
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src, dst, current_transfer_len);
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mic_dma_hw_ring_inc_head(ch);
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len -= current_transfer_len;
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dst = dst + current_transfer_len;
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src = src + current_transfer_len;
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} while (len > 0);
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return 0;
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}
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/* It's a h/w quirk and h/w needs 2 status descriptors for every status desc */
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static void mic_dma_prog_intr(struct mic_dma_chan *ch)
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{
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mic_dma_prep_status_desc(&ch->desc_ring[ch->head], 0,
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ch->status_dest_micpa, false);
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mic_dma_hw_ring_inc_head(ch);
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mic_dma_prep_status_desc(&ch->desc_ring[ch->head], 0,
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ch->status_dest_micpa, true);
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mic_dma_hw_ring_inc_head(ch);
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}
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/* Wrapper function to program memcpy descriptors/status descriptors */
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static int mic_dma_do_dma(struct mic_dma_chan *ch, int flags, dma_addr_t src,
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dma_addr_t dst, size_t len)
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{
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if (-ENOMEM == mic_dma_prog_memcpy_desc(ch, src, dst, len))
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return -ENOMEM;
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/* Above mic_dma_prog_memcpy_desc() makes sure we have enough space */
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if (flags & DMA_PREP_FENCE) {
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mic_dma_prep_status_desc(&ch->desc_ring[ch->head], 0,
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ch->status_dest_micpa, false);
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mic_dma_hw_ring_inc_head(ch);
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}
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if (flags & DMA_PREP_INTERRUPT)
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mic_dma_prog_intr(ch);
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return 0;
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}
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static inline void mic_dma_issue_pending(struct dma_chan *ch)
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{
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struct mic_dma_chan *mic_ch = to_mic_dma_chan(ch);
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spin_lock(&mic_ch->issue_lock);
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/*
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* Write to head triggers h/w to act on the descriptors.
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* On MIC, writing the same head value twice causes
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* a h/w error. On second write, h/w assumes we filled
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* the entire ring & overwrote some of the descriptors.
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*/
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if (mic_ch->issued == mic_ch->submitted)
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goto out;
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mic_ch->issued = mic_ch->submitted;
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/*
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* make descriptor updates visible before advancing head,
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* this is purposefully not smp_wmb() since we are also
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* publishing the descriptor updates to a dma device
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*/
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wmb();
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mic_dma_write_reg(mic_ch, MIC_DMA_REG_DHPR, mic_ch->issued);
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out:
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spin_unlock(&mic_ch->issue_lock);
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}
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static inline void mic_dma_update_pending(struct mic_dma_chan *ch)
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{
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if (mic_dma_ring_count(ch->issued, ch->submitted)
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> mic_dma_pending_level)
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mic_dma_issue_pending(&ch->api_ch);
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}
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static dma_cookie_t mic_dma_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
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{
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struct mic_dma_chan *mic_ch = to_mic_dma_chan(tx->chan);
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dma_cookie_t cookie;
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dma_cookie_assign(tx);
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cookie = tx->cookie;
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/*
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* We need an smp write barrier here because another CPU might see
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* an update to submitted and update h/w head even before we
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* assigned a cookie to this tx.
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*/
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smp_wmb();
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mic_ch->submitted = mic_ch->head;
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spin_unlock(&mic_ch->prep_lock);
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mic_dma_update_pending(mic_ch);
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return cookie;
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}
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static inline struct dma_async_tx_descriptor *
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allocate_tx(struct mic_dma_chan *ch)
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{
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u32 idx = mic_dma_hw_ring_dec(ch->head);
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struct dma_async_tx_descriptor *tx = &ch->tx_array[idx];
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dma_async_tx_descriptor_init(tx, &ch->api_ch);
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tx->tx_submit = mic_dma_tx_submit_unlock;
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return tx;
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}
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/*
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* Prepare a memcpy descriptor to be added to the ring.
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* Note that the temporary descriptor adds an extra overhead of copying the
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* descriptor to ring. So, we copy directly to the descriptor ring
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*/
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static struct dma_async_tx_descriptor *
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mic_dma_prep_memcpy_lock(struct dma_chan *ch, dma_addr_t dma_dest,
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dma_addr_t dma_src, size_t len, unsigned long flags)
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{
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struct mic_dma_chan *mic_ch = to_mic_dma_chan(ch);
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struct device *dev = mic_dma_ch_to_device(mic_ch);
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int result;
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if (!len && !flags)
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return NULL;
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spin_lock(&mic_ch->prep_lock);
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result = mic_dma_do_dma(mic_ch, flags, dma_src, dma_dest, len);
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if (result >= 0)
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return allocate_tx(mic_ch);
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dev_err(dev, "Error enqueueing dma, error=%d\n", result);
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spin_unlock(&mic_ch->prep_lock);
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return NULL;
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}
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static struct dma_async_tx_descriptor *
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mic_dma_prep_interrupt_lock(struct dma_chan *ch, unsigned long flags)
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{
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struct mic_dma_chan *mic_ch = to_mic_dma_chan(ch);
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int ret;
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spin_lock(&mic_ch->prep_lock);
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ret = mic_dma_do_dma(mic_ch, flags, 0, 0, 0);
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if (!ret)
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return allocate_tx(mic_ch);
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spin_unlock(&mic_ch->prep_lock);
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return NULL;
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}
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/* Return the status of the transaction */
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static enum dma_status
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mic_dma_tx_status(struct dma_chan *ch, dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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{
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struct mic_dma_chan *mic_ch = to_mic_dma_chan(ch);
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if (DMA_COMPLETE != dma_cookie_status(ch, cookie, txstate))
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mic_dma_cleanup(mic_ch);
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return dma_cookie_status(ch, cookie, txstate);
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}
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static irqreturn_t mic_dma_thread_fn(int irq, void *data)
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{
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mic_dma_cleanup((struct mic_dma_chan *)data);
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return IRQ_HANDLED;
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}
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static irqreturn_t mic_dma_intr_handler(int irq, void *data)
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{
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struct mic_dma_chan *ch = ((struct mic_dma_chan *)data);
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mic_dma_ack_interrupt(ch);
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return IRQ_WAKE_THREAD;
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}
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static int mic_dma_alloc_desc_ring(struct mic_dma_chan *ch)
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{
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u64 desc_ring_size = MIC_DMA_DESC_RX_SIZE * sizeof(*ch->desc_ring);
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struct device *dev = &to_mbus_device(ch)->dev;
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desc_ring_size = ALIGN(desc_ring_size, MIC_DMA_ALIGN_BYTES);
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ch->desc_ring = kzalloc(desc_ring_size, GFP_KERNEL);
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if (!ch->desc_ring)
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return -ENOMEM;
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ch->desc_ring_micpa = dma_map_single(dev, ch->desc_ring,
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desc_ring_size, DMA_BIDIRECTIONAL);
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if (dma_mapping_error(dev, ch->desc_ring_micpa))
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goto map_error;
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ch->tx_array = vzalloc(MIC_DMA_DESC_RX_SIZE * sizeof(*ch->tx_array));
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if (!ch->tx_array)
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goto tx_error;
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return 0;
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tx_error:
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dma_unmap_single(dev, ch->desc_ring_micpa, desc_ring_size,
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DMA_BIDIRECTIONAL);
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map_error:
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kfree(ch->desc_ring);
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return -ENOMEM;
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}
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static void mic_dma_free_desc_ring(struct mic_dma_chan *ch)
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{
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u64 desc_ring_size = MIC_DMA_DESC_RX_SIZE * sizeof(*ch->desc_ring);
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vfree(ch->tx_array);
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desc_ring_size = ALIGN(desc_ring_size, MIC_DMA_ALIGN_BYTES);
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dma_unmap_single(&to_mbus_device(ch)->dev, ch->desc_ring_micpa,
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desc_ring_size, DMA_BIDIRECTIONAL);
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kfree(ch->desc_ring);
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ch->desc_ring = NULL;
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}
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static void mic_dma_free_status_dest(struct mic_dma_chan *ch)
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{
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dma_unmap_single(&to_mbus_device(ch)->dev, ch->status_dest_micpa,
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L1_CACHE_BYTES, DMA_BIDIRECTIONAL);
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kfree(ch->status_dest);
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}
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static int mic_dma_alloc_status_dest(struct mic_dma_chan *ch)
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{
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struct device *dev = &to_mbus_device(ch)->dev;
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ch->status_dest = kzalloc(L1_CACHE_BYTES, GFP_KERNEL);
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if (!ch->status_dest)
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return -ENOMEM;
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ch->status_dest_micpa = dma_map_single(dev, ch->status_dest,
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L1_CACHE_BYTES, DMA_BIDIRECTIONAL);
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if (dma_mapping_error(dev, ch->status_dest_micpa)) {
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kfree(ch->status_dest);
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ch->status_dest = NULL;
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return -ENOMEM;
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}
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return 0;
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}
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static int mic_dma_check_chan(struct mic_dma_chan *ch)
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{
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if (mic_dma_read_reg(ch, MIC_DMA_REG_DCHERR) ||
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mic_dma_read_reg(ch, MIC_DMA_REG_DSTAT) & MIC_DMA_CHAN_QUIESCE) {
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mic_dma_disable_chan(ch);
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mic_dma_chan_mask_intr(ch);
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dev_err(mic_dma_ch_to_device(ch),
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"%s %d error setting up mic dma chan %d\n",
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__func__, __LINE__, ch->ch_num);
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return -EBUSY;
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}
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return 0;
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}
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static int mic_dma_chan_setup(struct mic_dma_chan *ch)
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{
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if (MIC_DMA_CHAN_MIC == ch->owner)
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mic_dma_chan_set_owner(ch);
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mic_dma_disable_chan(ch);
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mic_dma_chan_mask_intr(ch);
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mic_dma_write_reg(ch, MIC_DMA_REG_DCHERRMSK, 0);
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mic_dma_chan_set_desc_ring(ch);
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ch->last_tail = mic_dma_read_reg(ch, MIC_DMA_REG_DTPR);
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ch->head = ch->last_tail;
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ch->issued = 0;
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mic_dma_chan_unmask_intr(ch);
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mic_dma_enable_chan(ch);
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return mic_dma_check_chan(ch);
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}
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static void mic_dma_chan_destroy(struct mic_dma_chan *ch)
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{
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mic_dma_disable_chan(ch);
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mic_dma_chan_mask_intr(ch);
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}
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static void mic_dma_unregister_dma_device(struct mic_dma_device *mic_dma_dev)
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{
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dma_async_device_unregister(&mic_dma_dev->dma_dev);
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}
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static int mic_dma_setup_irq(struct mic_dma_chan *ch)
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{
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ch->cookie =
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to_mbus_hw_ops(ch)->request_threaded_irq(to_mbus_device(ch),
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mic_dma_intr_handler, mic_dma_thread_fn,
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"mic dma_channel", ch, ch->ch_num);
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if (IS_ERR(ch->cookie))
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return IS_ERR(ch->cookie);
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return 0;
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}
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static inline void mic_dma_free_irq(struct mic_dma_chan *ch)
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{
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to_mbus_hw_ops(ch)->free_irq(to_mbus_device(ch), ch->cookie, ch);
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}
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static int mic_dma_chan_init(struct mic_dma_chan *ch)
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{
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int ret = mic_dma_alloc_desc_ring(ch);
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if (ret)
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goto ring_error;
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ret = mic_dma_alloc_status_dest(ch);
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if (ret)
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goto status_error;
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ret = mic_dma_chan_setup(ch);
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if (ret)
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goto chan_error;
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return ret;
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chan_error:
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mic_dma_free_status_dest(ch);
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status_error:
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mic_dma_free_desc_ring(ch);
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ring_error:
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return ret;
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}
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static int mic_dma_drain_chan(struct mic_dma_chan *ch)
|
|
{
|
|
struct dma_async_tx_descriptor *tx;
|
|
int err = 0;
|
|
dma_cookie_t cookie;
|
|
|
|
tx = mic_dma_prep_memcpy_lock(&ch->api_ch, 0, 0, 0, DMA_PREP_FENCE);
|
|
if (!tx) {
|
|
err = -ENOMEM;
|
|
goto error;
|
|
}
|
|
|
|
cookie = tx->tx_submit(tx);
|
|
if (dma_submit_error(cookie))
|
|
err = -ENOMEM;
|
|
else
|
|
err = dma_sync_wait(&ch->api_ch, cookie);
|
|
if (err) {
|
|
dev_err(mic_dma_ch_to_device(ch), "%s %d TO chan 0x%x\n",
|
|
__func__, __LINE__, ch->ch_num);
|
|
err = -EIO;
|
|
}
|
|
error:
|
|
mic_dma_cleanup(ch);
|
|
return err;
|
|
}
|
|
|
|
static inline void mic_dma_chan_uninit(struct mic_dma_chan *ch)
|
|
{
|
|
mic_dma_chan_destroy(ch);
|
|
mic_dma_cleanup(ch);
|
|
mic_dma_free_status_dest(ch);
|
|
mic_dma_free_desc_ring(ch);
|
|
}
|
|
|
|
static int mic_dma_init(struct mic_dma_device *mic_dma_dev,
|
|
enum mic_dma_chan_owner owner)
|
|
{
|
|
int i, first_chan = mic_dma_dev->start_ch;
|
|
struct mic_dma_chan *ch;
|
|
int ret;
|
|
|
|
for (i = first_chan; i < first_chan + MIC_DMA_NUM_CHAN; i++) {
|
|
unsigned long data;
|
|
ch = &mic_dma_dev->mic_ch[i];
|
|
data = (unsigned long)ch;
|
|
ch->ch_num = i;
|
|
ch->owner = owner;
|
|
spin_lock_init(&ch->cleanup_lock);
|
|
spin_lock_init(&ch->prep_lock);
|
|
spin_lock_init(&ch->issue_lock);
|
|
ret = mic_dma_setup_irq(ch);
|
|
if (ret)
|
|
goto error;
|
|
}
|
|
return 0;
|
|
error:
|
|
for (i = i - 1; i >= first_chan; i--)
|
|
mic_dma_free_irq(ch);
|
|
return ret;
|
|
}
|
|
|
|
static void mic_dma_uninit(struct mic_dma_device *mic_dma_dev)
|
|
{
|
|
int i, first_chan = mic_dma_dev->start_ch;
|
|
struct mic_dma_chan *ch;
|
|
|
|
for (i = first_chan; i < first_chan + MIC_DMA_NUM_CHAN; i++) {
|
|
ch = &mic_dma_dev->mic_ch[i];
|
|
mic_dma_free_irq(ch);
|
|
}
|
|
}
|
|
|
|
static int mic_dma_alloc_chan_resources(struct dma_chan *ch)
|
|
{
|
|
int ret = mic_dma_chan_init(to_mic_dma_chan(ch));
|
|
if (ret)
|
|
return ret;
|
|
return MIC_DMA_DESC_RX_SIZE;
|
|
}
|
|
|
|
static void mic_dma_free_chan_resources(struct dma_chan *ch)
|
|
{
|
|
struct mic_dma_chan *mic_ch = to_mic_dma_chan(ch);
|
|
mic_dma_drain_chan(mic_ch);
|
|
mic_dma_chan_uninit(mic_ch);
|
|
}
|
|
|
|
/* Set the fn. handlers and register the dma device with dma api */
|
|
static int mic_dma_register_dma_device(struct mic_dma_device *mic_dma_dev,
|
|
enum mic_dma_chan_owner owner)
|
|
{
|
|
int i, first_chan = mic_dma_dev->start_ch;
|
|
|
|
dma_cap_zero(mic_dma_dev->dma_dev.cap_mask);
|
|
/*
|
|
* This dma engine is not capable of host memory to host memory
|
|
* transfers
|
|
*/
|
|
dma_cap_set(DMA_MEMCPY, mic_dma_dev->dma_dev.cap_mask);
|
|
|
|
if (MIC_DMA_CHAN_HOST == owner)
|
|
dma_cap_set(DMA_PRIVATE, mic_dma_dev->dma_dev.cap_mask);
|
|
mic_dma_dev->dma_dev.device_alloc_chan_resources =
|
|
mic_dma_alloc_chan_resources;
|
|
mic_dma_dev->dma_dev.device_free_chan_resources =
|
|
mic_dma_free_chan_resources;
|
|
mic_dma_dev->dma_dev.device_tx_status = mic_dma_tx_status;
|
|
mic_dma_dev->dma_dev.device_prep_dma_memcpy = mic_dma_prep_memcpy_lock;
|
|
mic_dma_dev->dma_dev.device_prep_dma_interrupt =
|
|
mic_dma_prep_interrupt_lock;
|
|
mic_dma_dev->dma_dev.device_issue_pending = mic_dma_issue_pending;
|
|
mic_dma_dev->dma_dev.copy_align = MIC_DMA_ALIGN_SHIFT;
|
|
INIT_LIST_HEAD(&mic_dma_dev->dma_dev.channels);
|
|
for (i = first_chan; i < first_chan + MIC_DMA_NUM_CHAN; i++) {
|
|
mic_dma_dev->mic_ch[i].api_ch.device = &mic_dma_dev->dma_dev;
|
|
dma_cookie_init(&mic_dma_dev->mic_ch[i].api_ch);
|
|
list_add_tail(&mic_dma_dev->mic_ch[i].api_ch.device_node,
|
|
&mic_dma_dev->dma_dev.channels);
|
|
}
|
|
return dma_async_device_register(&mic_dma_dev->dma_dev);
|
|
}
|
|
|
|
/*
|
|
* Initializes dma channels and registers the dma device with the
|
|
* dma engine api.
|
|
*/
|
|
static struct mic_dma_device *mic_dma_dev_reg(struct mbus_device *mbdev,
|
|
enum mic_dma_chan_owner owner)
|
|
{
|
|
struct mic_dma_device *mic_dma_dev;
|
|
int ret;
|
|
struct device *dev = &mbdev->dev;
|
|
|
|
mic_dma_dev = kzalloc(sizeof(*mic_dma_dev), GFP_KERNEL);
|
|
if (!mic_dma_dev) {
|
|
ret = -ENOMEM;
|
|
goto alloc_error;
|
|
}
|
|
mic_dma_dev->mbdev = mbdev;
|
|
mic_dma_dev->dma_dev.dev = dev;
|
|
mic_dma_dev->mmio = mbdev->mmio_va;
|
|
if (MIC_DMA_CHAN_HOST == owner) {
|
|
mic_dma_dev->start_ch = 0;
|
|
mic_dma_dev->max_xfer_size = MIC_DMA_MAX_XFER_SIZE_HOST;
|
|
} else {
|
|
mic_dma_dev->start_ch = 4;
|
|
mic_dma_dev->max_xfer_size = MIC_DMA_MAX_XFER_SIZE_CARD;
|
|
}
|
|
ret = mic_dma_init(mic_dma_dev, owner);
|
|
if (ret)
|
|
goto init_error;
|
|
ret = mic_dma_register_dma_device(mic_dma_dev, owner);
|
|
if (ret)
|
|
goto reg_error;
|
|
return mic_dma_dev;
|
|
reg_error:
|
|
mic_dma_uninit(mic_dma_dev);
|
|
init_error:
|
|
kfree(mic_dma_dev);
|
|
mic_dma_dev = NULL;
|
|
alloc_error:
|
|
dev_err(dev, "Error at %s %d ret=%d\n", __func__, __LINE__, ret);
|
|
return mic_dma_dev;
|
|
}
|
|
|
|
static void mic_dma_dev_unreg(struct mic_dma_device *mic_dma_dev)
|
|
{
|
|
mic_dma_unregister_dma_device(mic_dma_dev);
|
|
mic_dma_uninit(mic_dma_dev);
|
|
kfree(mic_dma_dev);
|
|
}
|
|
|
|
/* DEBUGFS CODE */
|
|
static int mic_dma_reg_seq_show(struct seq_file *s, void *pos)
|
|
{
|
|
struct mic_dma_device *mic_dma_dev = s->private;
|
|
int i, chan_num, first_chan = mic_dma_dev->start_ch;
|
|
struct mic_dma_chan *ch;
|
|
|
|
seq_printf(s, "SBOX_DCR: %#x\n",
|
|
mic_dma_mmio_read(&mic_dma_dev->mic_ch[first_chan],
|
|
MIC_DMA_SBOX_BASE + MIC_DMA_SBOX_DCR));
|
|
seq_puts(s, "DMA Channel Registers\n");
|
|
seq_printf(s, "%-10s| %-10s %-10s %-10s %-10s %-10s",
|
|
"Channel", "DCAR", "DTPR", "DHPR", "DRAR_HI", "DRAR_LO");
|
|
seq_printf(s, " %-11s %-14s %-10s\n", "DCHERR", "DCHERRMSK", "DSTAT");
|
|
for (i = first_chan; i < first_chan + MIC_DMA_NUM_CHAN; i++) {
|
|
ch = &mic_dma_dev->mic_ch[i];
|
|
chan_num = ch->ch_num;
|
|
seq_printf(s, "%-10i| %-#10x %-#10x %-#10x %-#10x",
|
|
chan_num,
|
|
mic_dma_read_reg(ch, MIC_DMA_REG_DCAR),
|
|
mic_dma_read_reg(ch, MIC_DMA_REG_DTPR),
|
|
mic_dma_read_reg(ch, MIC_DMA_REG_DHPR),
|
|
mic_dma_read_reg(ch, MIC_DMA_REG_DRAR_HI));
|
|
seq_printf(s, " %-#10x %-#10x %-#14x %-#10x\n",
|
|
mic_dma_read_reg(ch, MIC_DMA_REG_DRAR_LO),
|
|
mic_dma_read_reg(ch, MIC_DMA_REG_DCHERR),
|
|
mic_dma_read_reg(ch, MIC_DMA_REG_DCHERRMSK),
|
|
mic_dma_read_reg(ch, MIC_DMA_REG_DSTAT));
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int mic_dma_reg_debug_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, mic_dma_reg_seq_show, inode->i_private);
|
|
}
|
|
|
|
static int mic_dma_reg_debug_release(struct inode *inode, struct file *file)
|
|
{
|
|
return single_release(inode, file);
|
|
}
|
|
|
|
static const struct file_operations mic_dma_reg_ops = {
|
|
.owner = THIS_MODULE,
|
|
.open = mic_dma_reg_debug_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = mic_dma_reg_debug_release
|
|
};
|
|
|
|
/* Debugfs parent dir */
|
|
static struct dentry *mic_dma_dbg;
|
|
|
|
static int mic_dma_driver_probe(struct mbus_device *mbdev)
|
|
{
|
|
struct mic_dma_device *mic_dma_dev;
|
|
enum mic_dma_chan_owner owner;
|
|
|
|
if (MBUS_DEV_DMA_MIC == mbdev->id.device)
|
|
owner = MIC_DMA_CHAN_MIC;
|
|
else
|
|
owner = MIC_DMA_CHAN_HOST;
|
|
|
|
mic_dma_dev = mic_dma_dev_reg(mbdev, owner);
|
|
dev_set_drvdata(&mbdev->dev, mic_dma_dev);
|
|
|
|
if (mic_dma_dbg) {
|
|
mic_dma_dev->dbg_dir = debugfs_create_dir(dev_name(&mbdev->dev),
|
|
mic_dma_dbg);
|
|
if (mic_dma_dev->dbg_dir)
|
|
debugfs_create_file("mic_dma_reg", 0444,
|
|
mic_dma_dev->dbg_dir, mic_dma_dev,
|
|
&mic_dma_reg_ops);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void mic_dma_driver_remove(struct mbus_device *mbdev)
|
|
{
|
|
struct mic_dma_device *mic_dma_dev;
|
|
|
|
mic_dma_dev = dev_get_drvdata(&mbdev->dev);
|
|
debugfs_remove_recursive(mic_dma_dev->dbg_dir);
|
|
mic_dma_dev_unreg(mic_dma_dev);
|
|
}
|
|
|
|
static struct mbus_device_id id_table[] = {
|
|
{MBUS_DEV_DMA_MIC, MBUS_DEV_ANY_ID},
|
|
{MBUS_DEV_DMA_HOST, MBUS_DEV_ANY_ID},
|
|
{0},
|
|
};
|
|
|
|
static struct mbus_driver mic_dma_driver = {
|
|
.driver.name = KBUILD_MODNAME,
|
|
.driver.owner = THIS_MODULE,
|
|
.id_table = id_table,
|
|
.probe = mic_dma_driver_probe,
|
|
.remove = mic_dma_driver_remove,
|
|
};
|
|
|
|
static int __init mic_x100_dma_init(void)
|
|
{
|
|
int rc = mbus_register_driver(&mic_dma_driver);
|
|
if (rc)
|
|
return rc;
|
|
mic_dma_dbg = debugfs_create_dir(KBUILD_MODNAME, NULL);
|
|
return 0;
|
|
}
|
|
|
|
static void __exit mic_x100_dma_exit(void)
|
|
{
|
|
debugfs_remove_recursive(mic_dma_dbg);
|
|
mbus_unregister_driver(&mic_dma_driver);
|
|
}
|
|
|
|
module_init(mic_x100_dma_init);
|
|
module_exit(mic_x100_dma_exit);
|
|
|
|
MODULE_DEVICE_TABLE(mbus, id_table);
|
|
MODULE_AUTHOR("Intel Corporation");
|
|
MODULE_DESCRIPTION("Intel(R) MIC X100 DMA Driver");
|
|
MODULE_LICENSE("GPL v2");
|