mirror of https://gitee.com/openkylin/linux.git
120 lines
3.8 KiB
Plaintext
120 lines
3.8 KiB
Plaintext
Specifying GPIO information for devices
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============================================
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1) gpios property
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-----------------
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Nodes that makes use of GPIOs should specify them using one or more
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properties, each containing a 'gpio-list':
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gpio-list ::= <single-gpio> [gpio-list]
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single-gpio ::= <gpio-phandle> <gpio-specifier>
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gpio-phandle : phandle to gpio controller node
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gpio-specifier : Array of #gpio-cells specifying specific gpio
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(controller specific)
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GPIO properties should be named "[<name>-]gpios". Exact
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meaning of each gpios property must be documented in the device tree
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binding for each device.
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For example, the following could be used to describe gpios pins to use
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as chip select lines; with chip selects 0, 1 and 3 populated, and chip
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select 2 left empty:
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gpio1: gpio1 {
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gpio-controller
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#gpio-cells = <2>;
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};
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gpio2: gpio2 {
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gpio-controller
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#gpio-cells = <1>;
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};
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[...]
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chipsel-gpios = <&gpio1 12 0>,
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<&gpio1 13 0>,
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<0>, /* holes are permitted, means no GPIO 2 */
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<&gpio2 2>;
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Note that gpio-specifier length is controller dependent. In the
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above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2
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only uses one.
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gpio-specifier may encode: bank, pin position inside the bank,
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whether pin is open-drain and whether pin is logically inverted.
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Exact meaning of each specifier cell is controller specific, and must
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be documented in the device tree binding for the device.
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Example of the node using GPIOs:
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node {
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gpios = <&qe_pio_e 18 0>;
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};
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In this example gpio-specifier is "18 0" and encodes GPIO pin number,
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and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
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2) gpio-controller nodes
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------------------------
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Every GPIO controller node must both an empty "gpio-controller"
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property, and have #gpio-cells contain the size of the gpio-specifier.
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Example of two SOC GPIO banks defined as gpio-controller nodes:
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qe_pio_a: gpio-controller@1400 {
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#gpio-cells = <2>;
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compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
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reg = <0x1400 0x18>;
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gpio-controller;
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};
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qe_pio_e: gpio-controller@1460 {
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#gpio-cells = <2>;
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compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
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reg = <0x1460 0x18>;
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gpio-controller;
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};
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2.1) gpio- and pin-controller interaction
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-----------------------------------------
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Some or all of the GPIOs provided by a GPIO controller may be routed to pins
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on the package via a pin controller. This allows muxing those pins between
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GPIO and other functions.
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It is useful to represent which GPIOs correspond to which pins on which pin
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controllers. The gpio-ranges property described below represents this, and
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contains information structures as follows:
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gpio-range-list ::= <single-gpio-range> [gpio-range-list]
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single-gpio-range ::=
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<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
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gpio-phandle : phandle to pin controller node.
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gpio-base : Base GPIO ID in the GPIO controller
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pinctrl-base : Base pinctrl pin ID in the pin controller
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count : The number of GPIOs/pins in this range
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The "pin controller node" mentioned above must conform to the bindings
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described in ../pinctrl/pinctrl-bindings.txt.
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Previous versions of this binding required all pin controller nodes that
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were referenced by any gpio-ranges property to contain a property named
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#gpio-range-cells with value <3>. This requirement is now deprecated.
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However, that property may still exist in older device trees for
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compatibility reasons, and would still be required even in new device
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trees that need to be compatible with older software.
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Example:
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qe_pio_e: gpio-controller@1460 {
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#gpio-cells = <2>;
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compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
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reg = <0x1460 0x18>;
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gpio-controller;
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gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
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};
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Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
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pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
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pins 50..59.
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