mirror of https://gitee.com/openkylin/linux.git
318 lines
11 KiB
C
318 lines
11 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_ucode.h"
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static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
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{
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DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
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DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
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DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
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DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
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DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
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DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
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DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
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DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
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DRM_DEBUG("ucode_array_offset_bytes: %u\n",
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le32_to_cpu(hdr->ucode_array_offset_bytes));
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DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
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}
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void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
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{
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uint16_t version_major = le16_to_cpu(hdr->header_version_major);
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uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
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DRM_DEBUG("MC\n");
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amdgpu_ucode_print_common_hdr(hdr);
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if (version_major == 1) {
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const struct mc_firmware_header_v1_0 *mc_hdr =
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container_of(hdr, struct mc_firmware_header_v1_0, header);
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DRM_DEBUG("io_debug_size_bytes: %u\n",
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le32_to_cpu(mc_hdr->io_debug_size_bytes));
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DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
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le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
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} else {
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DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
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}
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}
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void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
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{
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uint16_t version_major = le16_to_cpu(hdr->header_version_major);
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uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
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DRM_DEBUG("SMC\n");
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amdgpu_ucode_print_common_hdr(hdr);
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if (version_major == 1) {
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const struct smc_firmware_header_v1_0 *smc_hdr =
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container_of(hdr, struct smc_firmware_header_v1_0, header);
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DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
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} else {
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DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
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}
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}
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void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
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{
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uint16_t version_major = le16_to_cpu(hdr->header_version_major);
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uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
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DRM_DEBUG("GFX\n");
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amdgpu_ucode_print_common_hdr(hdr);
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if (version_major == 1) {
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const struct gfx_firmware_header_v1_0 *gfx_hdr =
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container_of(hdr, struct gfx_firmware_header_v1_0, header);
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DRM_DEBUG("ucode_feature_version: %u\n",
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le32_to_cpu(gfx_hdr->ucode_feature_version));
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DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
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DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
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} else {
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DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
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}
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}
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void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
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{
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uint16_t version_major = le16_to_cpu(hdr->header_version_major);
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uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
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DRM_DEBUG("RLC\n");
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amdgpu_ucode_print_common_hdr(hdr);
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if (version_major == 1) {
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const struct rlc_firmware_header_v1_0 *rlc_hdr =
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container_of(hdr, struct rlc_firmware_header_v1_0, header);
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DRM_DEBUG("ucode_feature_version: %u\n",
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le32_to_cpu(rlc_hdr->ucode_feature_version));
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DRM_DEBUG("save_and_restore_offset: %u\n",
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le32_to_cpu(rlc_hdr->save_and_restore_offset));
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DRM_DEBUG("clear_state_descriptor_offset: %u\n",
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le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
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DRM_DEBUG("avail_scratch_ram_locations: %u\n",
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le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
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DRM_DEBUG("master_pkt_description_offset: %u\n",
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le32_to_cpu(rlc_hdr->master_pkt_description_offset));
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} else if (version_major == 2) {
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const struct rlc_firmware_header_v2_0 *rlc_hdr =
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container_of(hdr, struct rlc_firmware_header_v2_0, header);
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DRM_DEBUG("ucode_feature_version: %u\n",
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le32_to_cpu(rlc_hdr->ucode_feature_version));
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DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
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DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
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DRM_DEBUG("save_and_restore_offset: %u\n",
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le32_to_cpu(rlc_hdr->save_and_restore_offset));
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DRM_DEBUG("clear_state_descriptor_offset: %u\n",
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le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
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DRM_DEBUG("avail_scratch_ram_locations: %u\n",
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le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
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DRM_DEBUG("reg_restore_list_size: %u\n",
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le32_to_cpu(rlc_hdr->reg_restore_list_size));
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DRM_DEBUG("reg_list_format_start: %u\n",
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le32_to_cpu(rlc_hdr->reg_list_format_start));
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DRM_DEBUG("reg_list_format_separate_start: %u\n",
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le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
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DRM_DEBUG("starting_offsets_start: %u\n",
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le32_to_cpu(rlc_hdr->starting_offsets_start));
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DRM_DEBUG("reg_list_format_size_bytes: %u\n",
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le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
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DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
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le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
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DRM_DEBUG("reg_list_size_bytes: %u\n",
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le32_to_cpu(rlc_hdr->reg_list_size_bytes));
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DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
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le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
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DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
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le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
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DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
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le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
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DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
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le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
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DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
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le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
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} else {
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DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
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}
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}
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void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
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{
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uint16_t version_major = le16_to_cpu(hdr->header_version_major);
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uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
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DRM_DEBUG("SDMA\n");
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amdgpu_ucode_print_common_hdr(hdr);
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if (version_major == 1) {
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const struct sdma_firmware_header_v1_0 *sdma_hdr =
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container_of(hdr, struct sdma_firmware_header_v1_0, header);
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DRM_DEBUG("ucode_feature_version: %u\n",
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le32_to_cpu(sdma_hdr->ucode_feature_version));
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DRM_DEBUG("ucode_change_version: %u\n",
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le32_to_cpu(sdma_hdr->ucode_change_version));
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DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
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DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
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if (version_minor >= 1) {
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const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
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container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
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DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
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}
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} else {
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DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
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version_major, version_minor);
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}
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}
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int amdgpu_ucode_validate(const struct firmware *fw)
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{
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const struct common_firmware_header *hdr =
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(const struct common_firmware_header *)fw->data;
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if (fw->size == le32_to_cpu(hdr->size_bytes))
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return 0;
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return -EINVAL;
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}
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bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
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uint16_t hdr_major, uint16_t hdr_minor)
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{
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if ((hdr->common.header_version_major == hdr_major) &&
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(hdr->common.header_version_minor == hdr_minor))
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return false;
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return true;
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}
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static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
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uint64_t mc_addr, void *kptr)
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{
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const struct common_firmware_header *header = NULL;
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if (NULL == ucode->fw)
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return 0;
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ucode->mc_addr = mc_addr;
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ucode->kaddr = kptr;
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header = (const struct common_firmware_header *)ucode->fw->data;
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memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
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le32_to_cpu(header->ucode_array_offset_bytes)),
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le32_to_cpu(header->ucode_size_bytes));
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return 0;
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}
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int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
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{
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struct amdgpu_bo **bo = &adev->firmware.fw_buf;
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uint64_t fw_mc_addr;
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void *fw_buf_ptr = NULL;
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uint64_t fw_offset = 0;
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int i, err;
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struct amdgpu_firmware_info *ucode = NULL;
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const struct common_firmware_header *header = NULL;
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err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
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AMDGPU_GEM_DOMAIN_GTT, 0, NULL, bo);
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if (err) {
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dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
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err = -ENOMEM;
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goto failed;
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}
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err = amdgpu_bo_reserve(*bo, false);
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if (err) {
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amdgpu_bo_unref(bo);
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dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
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goto failed;
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}
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err = amdgpu_bo_pin(*bo, AMDGPU_GEM_DOMAIN_GTT, &fw_mc_addr);
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if (err) {
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amdgpu_bo_unreserve(*bo);
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amdgpu_bo_unref(bo);
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dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
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goto failed;
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}
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err = amdgpu_bo_kmap(*bo, &fw_buf_ptr);
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if (err) {
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dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
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amdgpu_bo_unpin(*bo);
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amdgpu_bo_unreserve(*bo);
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amdgpu_bo_unref(bo);
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goto failed;
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}
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amdgpu_bo_unreserve(*bo);
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fw_offset = 0;
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for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) {
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ucode = &adev->firmware.ucode[i];
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if (ucode->fw) {
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header = (const struct common_firmware_header *)ucode->fw->data;
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amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset,
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fw_buf_ptr + fw_offset);
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fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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}
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}
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failed:
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if (err)
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adev->firmware.smu_load = false;
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return err;
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}
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int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
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{
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int i;
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struct amdgpu_firmware_info *ucode = NULL;
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for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) {
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ucode = &adev->firmware.ucode[i];
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if (ucode->fw) {
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ucode->mc_addr = 0;
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ucode->kaddr = NULL;
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}
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}
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amdgpu_bo_unref(&adev->firmware.fw_buf);
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adev->firmware.fw_buf = NULL;
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return 0;
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}
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