mirror of https://gitee.com/openkylin/linux.git
216 lines
9.0 KiB
C
216 lines
9.0 KiB
C
/*
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* Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
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* Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/*
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* Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
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*/
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#define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */
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#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */
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#define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */
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#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */
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#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
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#define AR5K_EEPROM_PROTECT 0x003f /* EEPROM protect status */
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#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */
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#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */
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#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */
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#define AR5K_EEPROM_PROTECT_WR_32_63 0x0008
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#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */
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#define AR5K_EEPROM_PROTECT_WR_64_127 0x0020
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#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */
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#define AR5K_EEPROM_PROTECT_WR_128_191 0x0080
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#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */
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#define AR5K_EEPROM_PROTECT_WR_192_207 0x0200
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#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */
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#define AR5K_EEPROM_PROTECT_WR_208_223 0x0800
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#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */
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#define AR5K_EEPROM_PROTECT_WR_224_239 0x2000
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#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */
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#define AR5K_EEPROM_PROTECT_WR_240_255 0x8000
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#define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */
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#define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */
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#define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE)
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#define AR5K_EEPROM_INFO_CKSUM 0xffff
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#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
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#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */
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#define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */
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#define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */
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#define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */
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#define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
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#define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain ee_cck_ofdm_power_delta (eeprom_read_modes) */
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#define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc*, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
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#define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */
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#define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */
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#define AR5K_EEPROM_VERSION_4_3 0x4003
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#define AR5K_EEPROM_VERSION_4_4 0x4004
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#define AR5K_EEPROM_VERSION_4_5 0x4005
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#define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */
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#define AR5K_EEPROM_VERSION_4_7 0x4007
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#define AR5K_EEPROM_MODE_11A 0
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#define AR5K_EEPROM_MODE_11B 1
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#define AR5K_EEPROM_MODE_11G 2
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#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */
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#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
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#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
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#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
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#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */
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#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */
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#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
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#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz (?) */
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#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */
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#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
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#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
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#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
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#define AR5K_EEPROM_RFKILL_POLARITY_S 1
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/* Newer EEPROMs are using a different offset */
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#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
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(((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
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#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
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#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff))
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#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff))
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/* calibration settings */
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#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
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#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
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#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
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#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */
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/* [3.1 - 3.3] */
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#define AR5K_EEPROM_OBDB0_2GHZ 0x00ec
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#define AR5K_EEPROM_OBDB1_2GHZ 0x00ed
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/* Misc values available since EEPROM 4.0 */
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#define AR5K_EEPROM_MISC0 0x00c4
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#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
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#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
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#define AR5K_EEPROM_MISC1 0x00c5
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#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
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#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
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/* Some EEPROM defines */
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#define AR5K_EEPROM_EEP_SCALE 100
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#define AR5K_EEPROM_EEP_DELTA 10
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#define AR5K_EEPROM_N_MODES 3
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#define AR5K_EEPROM_N_5GHZ_CHAN 10
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#define AR5K_EEPROM_N_2GHZ_CHAN 3
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#define AR5K_EEPROM_MAX_CHAN 10
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#define AR5K_EEPROM_N_PCDAC 11
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#define AR5K_EEPROM_N_TEST_FREQ 8
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#define AR5K_EEPROM_N_EDGES 8
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#define AR5K_EEPROM_N_INTERCEPTS 11
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#define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
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#define AR5K_EEPROM_PCDAC_M 0x3f
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#define AR5K_EEPROM_PCDAC_START 1
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#define AR5K_EEPROM_PCDAC_STOP 63
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#define AR5K_EEPROM_PCDAC_STEP 1
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#define AR5K_EEPROM_NON_EDGE_M 0x40
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#define AR5K_EEPROM_CHANNEL_POWER 8
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#define AR5K_EEPROM_N_OBDB 4
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#define AR5K_EEPROM_OBDB_DIS 0xffff
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#define AR5K_EEPROM_CHANNEL_DIS 0xff
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#define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
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#define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32)
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#define AR5K_EEPROM_MAX_CTLS 32
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#define AR5K_EEPROM_N_XPD_PER_CHANNEL 4
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#define AR5K_EEPROM_N_XPD0_POINTS 4
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#define AR5K_EEPROM_N_XPD3_POINTS 3
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#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
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#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
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#define AR5K_EEPROM_POWER_M 0x3f
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#define AR5K_EEPROM_POWER_MIN 0
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#define AR5K_EEPROM_POWER_MAX 3150
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#define AR5K_EEPROM_POWER_STEP 50
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#define AR5K_EEPROM_POWER_TABLE_SIZE 64
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#define AR5K_EEPROM_N_POWER_LOC_11B 4
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#define AR5K_EEPROM_N_POWER_LOC_11G 6
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#define AR5K_EEPROM_I_GAIN 10
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#define AR5K_EEPROM_CCK_OFDM_DELTA 15
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#define AR5K_EEPROM_N_IQ_CAL 2
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#define AR5K_EEPROM_READ(_o, _v) do { \
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ret = ath5k_hw_eeprom_read(ah, (_o), &(_v)); \
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if (ret) \
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return ret; \
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} while (0)
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#define AR5K_EEPROM_READ_HDR(_o, _v) \
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AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \
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/* Struct to hold EEPROM calibration data */
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struct ath5k_eeprom_info {
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u16 ee_magic;
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u16 ee_protect;
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u16 ee_regdomain;
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u16 ee_version;
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u16 ee_header;
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u16 ee_ant_gain;
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u16 ee_misc0;
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u16 ee_misc1;
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u16 ee_cck_ofdm_gain_delta;
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u16 ee_cck_ofdm_power_delta;
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u16 ee_scaled_cck_delta;
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/* Used for tx thermal adjustment (eeprom_init, rfregs) */
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u16 ee_tx_clip;
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u16 ee_pwd_84;
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u16 ee_pwd_90;
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u16 ee_gain_select;
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/* RF Calibration settings (reset, rfregs) */
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u16 ee_i_cal[AR5K_EEPROM_N_MODES];
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u16 ee_q_cal[AR5K_EEPROM_N_MODES];
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u16 ee_fixed_bias[AR5K_EEPROM_N_MODES];
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u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES];
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u16 ee_xr_power[AR5K_EEPROM_N_MODES];
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u16 ee_switch_settling[AR5K_EEPROM_N_MODES];
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u16 ee_ant_tx_rx[AR5K_EEPROM_N_MODES];
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u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
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u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
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u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
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u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
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u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
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u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
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u16 ee_thr_62[AR5K_EEPROM_N_MODES];
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u16 ee_xlna_gain[AR5K_EEPROM_N_MODES];
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u16 ee_xpd[AR5K_EEPROM_N_MODES];
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u16 ee_x_gain[AR5K_EEPROM_N_MODES];
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u16 ee_i_gain[AR5K_EEPROM_N_MODES];
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u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
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/* Unused */
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u16 ee_false_detect[AR5K_EEPROM_N_MODES];
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u16 ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN];
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u16 ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; /*empty*/
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/* Conformance test limits (Unused) */
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u16 ee_ctls;
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u16 ee_ctl[AR5K_EEPROM_MAX_CTLS];
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/* Noise Floor Calibration settings */
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s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
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s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES];
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s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES];
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};
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