mirror of https://gitee.com/openkylin/linux.git
177 lines
6.0 KiB
C
177 lines
6.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Marvell 88E6xxx SERDES manipulation, via SMI bus
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
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*/
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#ifndef _MV88E6XXX_SERDES_H
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#define _MV88E6XXX_SERDES_H
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#include "chip.h"
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#define MV88E6352_ADDR_SERDES 0x0f
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#define MV88E6352_SERDES_PAGE_FIBER 0x01
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#define MV88E6352_SERDES_IRQ 0x0b
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#define MV88E6352_SERDES_INT_ENABLE 0x12
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#define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14)
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#define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13)
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#define MV88E6352_SERDES_INT_PAGE_RX BIT(12)
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#define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11)
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#define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10)
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#define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9)
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#define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8)
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#define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7)
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#define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4)
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#define MV88E6352_SERDES_INT_STATUS 0x13
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#define MV88E6341_PORT5_LANE 0x15
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#define MV88E6390_PORT9_LANE0 0x09
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#define MV88E6390_PORT9_LANE1 0x12
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#define MV88E6390_PORT9_LANE2 0x13
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#define MV88E6390_PORT9_LANE3 0x14
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#define MV88E6390_PORT10_LANE0 0x0a
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#define MV88E6390_PORT10_LANE1 0x15
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#define MV88E6390_PORT10_LANE2 0x16
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#define MV88E6390_PORT10_LANE3 0x17
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/* 10GBASE-R and 10GBASE-X4/X2 */
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#define MV88E6390_PCS_CONTROL_1 0x1000
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#define MV88E6390_PCS_CONTROL_1_RESET BIT(15)
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#define MV88E6390_PCS_CONTROL_1_LOOPBACK BIT(14)
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#define MV88E6390_PCS_CONTROL_1_SPEED BIT(13)
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#define MV88E6390_PCS_CONTROL_1_PDOWN BIT(11)
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/* 1000BASE-X and SGMII */
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#define MV88E6390_SGMII_CONTROL 0x2000
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#define MV88E6390_SGMII_CONTROL_RESET BIT(15)
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#define MV88E6390_SGMII_CONTROL_LOOPBACK BIT(14)
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#define MV88E6390_SGMII_CONTROL_PDOWN BIT(11)
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#define MV88E6390_SGMII_STATUS 0x2001
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#define MV88E6390_SGMII_STATUS_AN_DONE BIT(5)
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#define MV88E6390_SGMII_STATUS_REMOTE_FAULT BIT(4)
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#define MV88E6390_SGMII_STATUS_LINK BIT(2)
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#define MV88E6390_SGMII_INT_ENABLE 0xa001
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#define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14)
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#define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13)
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#define MV88E6390_SGMII_INT_PAGE_RX BIT(12)
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#define MV88E6390_SGMII_INT_AN_COMPLETE BIT(11)
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#define MV88E6390_SGMII_INT_LINK_DOWN BIT(10)
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#define MV88E6390_SGMII_INT_LINK_UP BIT(9)
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#define MV88E6390_SGMII_INT_SYMBOL_ERROR BIT(8)
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#define MV88E6390_SGMII_INT_FALSE_CARRIER BIT(7)
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#define MV88E6390_SGMII_INT_STATUS 0xa002
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#define MV88E6390_SGMII_PHY_STATUS 0xa003
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#define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK GENMASK(15, 14)
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#define MV88E6390_SGMII_PHY_STATUS_SPEED_1000 0x8000
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#define MV88E6390_SGMII_PHY_STATUS_SPEED_100 0x4000
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#define MV88E6390_SGMII_PHY_STATUS_SPEED_10 0x0000
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#define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL BIT(13)
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#define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
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#define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10)
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/* Packet generator pad packet checker */
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#define MV88E6390_PG_CONTROL 0xf010
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#define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0)
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u8 mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
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u8 mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
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u8 mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
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u8 mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
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unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
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int port);
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unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
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int port);
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int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
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bool on);
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int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
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bool on);
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int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane,
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bool enable);
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int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane,
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bool enable);
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irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
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u8 lane);
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irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
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u8 lane);
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int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
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int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
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int port, uint8_t *data);
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int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
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uint64_t *data);
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int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
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int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
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int port, uint8_t *data);
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int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
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uint64_t *data);
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/* Return the (first) SERDES lane address a port is using, 0 otherwise. */
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static inline u8 mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
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int port)
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{
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if (!chip->info->ops->serdes_get_lane)
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return 0;
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return chip->info->ops->serdes_get_lane(chip, port);
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}
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static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip,
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int port, u8 lane)
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{
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if (!chip->info->ops->serdes_power)
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return -EOPNOTSUPP;
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return chip->info->ops->serdes_power(chip, port, lane, true);
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}
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static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip,
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int port, u8 lane)
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{
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if (!chip->info->ops->serdes_power)
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return -EOPNOTSUPP;
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return chip->info->ops->serdes_power(chip, port, lane, false);
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}
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static inline unsigned int
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mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
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{
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if (!chip->info->ops->serdes_irq_mapping)
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return 0;
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return chip->info->ops->serdes_irq_mapping(chip, port);
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}
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static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip,
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int port, u8 lane)
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{
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if (!chip->info->ops->serdes_irq_enable)
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return -EOPNOTSUPP;
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return chip->info->ops->serdes_irq_enable(chip, port, lane, true);
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}
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static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip,
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int port, u8 lane)
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{
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if (!chip->info->ops->serdes_irq_enable)
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return -EOPNOTSUPP;
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return chip->info->ops->serdes_irq_enable(chip, port, lane, false);
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}
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static inline irqreturn_t
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mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, u8 lane)
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{
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if (!chip->info->ops->serdes_irq_status)
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return IRQ_NONE;
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return chip->info->ops->serdes_irq_status(chip, port, lane);
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}
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#endif
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