mirror of https://gitee.com/openkylin/linux.git
5e33ebff7e
All device trees currently in mainline specify the time clock parent
using the assigned-clocks/assigned-clock-parents method, there is no
need to statically assign the parent in the core clock driver.
Also all current boards provide an Ethernet reference clock for the
PHY externally, hence configuring the internal PHY reference clock.
Furthermore, and the actual driver of this patch, specify ethernet
related parents at that early point in boot leads to a warning:
bad: scheduling from the idle thread!
The reason for the warning is that setting the parent enables the ENET
PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can
cause clk_pllv3_wait_lock to sleep. See also:
commit
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| .. | ||
| Makefile | ||
| clk-busy.c | ||
| clk-cpu.c | ||
| clk-fixup-div.c | ||
| clk-fixup-mux.c | ||
| clk-gate-exclusive.c | ||
| clk-gate2.c | ||
| clk-imx1.c | ||
| clk-imx6q.c | ||
| clk-imx6sl.c | ||
| clk-imx6sx.c | ||
| clk-imx6ul.c | ||
| clk-imx7d.c | ||
| clk-imx21.c | ||
| clk-imx25.c | ||
| clk-imx27.c | ||
| clk-imx31.c | ||
| clk-imx35.c | ||
| clk-imx51-imx53.c | ||
| clk-pfd.c | ||
| clk-pllv1.c | ||
| clk-pllv2.c | ||
| clk-pllv3.c | ||
| clk-vf610.c | ||
| clk.c | ||
| clk.h | ||